SGLS346A June   2006  – August 2025 TPS73201-EP , TPS73215-EP , TPS73216-EP , TPS73218-EP , TPS73225-EP , TPS73230-EP , TPS73233-EP , TPS73250-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2.     Power Dissipation Ratings
    3. 5.2 Electrical Characteristics
    4. 5.3 Typical Characteristics
  7. 6 Functional Block Diagrams
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Input and Output Capacitor Requirements
      2. 7.1.2  Output Noise
      3. 7.1.3  Board Layout Recommendation to Improve PSRR and Noise Performance
      4. 7.1.4  Internal Current Limit
      5. 7.1.5  Shutdown
      6. 7.1.6  Dropout Voltage
      7. 7.1.7  Transient Response
      8. 7.1.8  Reverse Current
      9. 7.1.9  Thermal Protection
      10. 7.1.10 Power Dissipation
      11. 7.1.11 Package Mounting
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1.1 Input and Output Capacitor Requirements

Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1 μF to 1 μF low ESR capacitor across the input supply near the regulator. This counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or the device is located several inches from the power source.

The TPS732xx-EP does not require an output capacitor for stability and has maximum phase margin with no capacitor. It is designed to be stable for all available types and values of capacitors. In applications where VIN – VOUT < 0.5 V and multiple low ESR capacitors are in parallel, ringing may occur when the product of COUT and total ESR drops below 50 nΩF. Total ESR includes all parasitic resistances, including capacitor ESR and board, socket, and solder joint resistance. In most applications, the sum of capacitor ESR and trace resistance will meet this requirement.