SGLS346A June   2006  – August 2025 TPS73201-EP , TPS73215-EP , TPS73216-EP , TPS73218-EP , TPS73225-EP , TPS73230-EP , TPS73233-EP , TPS73250-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2.     Power Dissipation Ratings
    3. 5.2 Electrical Characteristics
    4. 5.3 Typical Characteristics
  7. 6 Functional Block Diagrams
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Input and Output Capacitor Requirements
      2. 7.1.2  Output Noise
      3. 7.1.3  Board Layout Recommendation to Improve PSRR and Noise Performance
      4. 7.1.4  Internal Current Limit
      5. 7.1.5  Shutdown
      6. 7.1.6  Dropout Voltage
      7. 7.1.7  Transient Response
      8. 7.1.8  Reverse Current
      9. 7.1.9  Thermal Protection
      10. 7.1.10 Power Dissipation
      11. 7.1.11 Package Mounting
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Power Dissipation Ratings

see (1)
BOARD PACKAGE RΘJC RΘJA DERATING FACTOR
ABOVE TA = 25°C		 TA ≤ 25°C
POWER RATING		 TA = 70°C
POWER RATING		 TA = 85°C
POWER RATING		 TA = 125°C
POWER RATING
Low-K(2) DBV 64°C/W 255°C/W 3.9 mW/°C 450 mW 275 mW 215 mW 58 mW
High-K(3) DBV 64°/W 180°C/W 5.6 mW/°C 638 mW 388 mW 305 mW 83 mW
(1) See Power Dissipation in the Application and Implementation section for more information related to thermal design.
(2) The JEDEC Low-K (1s) board design used to derive this data was a 3 inch × 3 inch, two-layer board with 2-ounce copper traces on top of the board.
(3) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch × 3 inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on the top and bottom of the board.