SBVS263B July   2017  – June 2025 TPS7A39

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Start-Up Characteristics
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Voltage Regulation
        1. 6.3.1.1 DC Regulation
        2. 6.3.1.2 AC and Transient Response
      2. 6.3.2 User-Settable Buffered Reference
      3. 6.3.3 Active Discharge
      4. 6.3.4 System Start-Up Controls
        1. 6.3.4.1 Start-Up Tracking
        2. 6.3.4.2 Sequencing
          1. 6.3.4.2.1 Enable (EN)
          2. 6.3.4.2.2 Undervoltage Lockout (UVLO) Control
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Setting the Output Voltages on Adjustable Devices
      2. 7.1.2  Capacitor Recommendations
      3. 7.1.3  Input and Output Capacitor (CINx and COUTx)
      4. 7.1.4  Feed-Forward Capacitor (CFFx)
      5. 7.1.5  Noise-Reduction and Soft-Start Capacitor (CNR/SS)
      6. 7.1.6  Buffered Reference Voltage
      7. 7.1.7  Overriding Internal Reference
      8. 7.1.8  Start-Up
        1. 7.1.8.1 Soft-Start Control (NR/SS)
          1. 7.1.8.1.1 In-Rush Current
        2. 7.1.8.2 Undervoltage Lockout (UVLOx) Control
      9. 7.1.9  AC and Transient Performance
        1. 7.1.9.1 Power-Supply Rejection Ratio (PSRR)
        2. 7.1.9.2 Channel-to-Channel Output Isolation and Crosstalk
        3. 7.1.9.3 Output Voltage Noise
        4. 7.1.9.4 Optimizing Noise and PSRR
        5. 7.1.9.5 Load Transient Response
      10. 7.1.10 DC Performance
        1. 7.1.10.1 Output Voltage Accuracy (VOUT x)
        2. 7.1.10.2 Dropout Voltage (VDO)
      11. 7.1.11 Reverse Current
      12. 7.1.12 Power Dissipation (PD)
        1. 7.1.12.1 Estimating Junction Temperature
    2. 7.2 Typical Applications
      1. 7.2.1 Design 1: Single-Ended to Differential Isolated Supply
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Switcher Choice
          2. 7.2.1.2.2 Full Bridge Rectifier With Center-Tapped Transformer
          3. 7.2.1.2.3 Total Solution Efficiency
          4. 7.2.1.2.4 Feedback Resistor Selection
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Design 2: Getting the Full Range of a SAR ADC
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Detailed Design Description
          1. 7.2.2.3.1 Regulation of –0.2V
          2. 7.2.2.3.2 Feedback Resistor Selection
        4. 7.2.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
        2. 7.4.1.2 Package Mounting
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Modules
        2. 8.1.1.2 Spice Models
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

at TJ = –40°C to +125°C, VINP(nom) = VOUTP(nom) + 1V or VIN(nom) = 3.3V (whichever is greater), VINN(nom) = VOUTN(nom) – 1V or VINN(nom) = –3.3V (whichever is less), VEN = VINP, IOUT = 1mA, CINx = 2.2μF, COUTx = 10μF, CFFx = CNR/SS = open, R1N = R2N = 10kΩ, and FBP tied to OUTP (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VINP Input voltage range, positive channel 3.3 33 V
VINN Input voltage range, negative channel –33 –3.3 V
VUVLOP(rising) Undervoltage lockout threshold,
positive channel		 VINP rising, VINN = –3.3V 1.4 3.1 V
VUVLOP(hys) Undervoltage lockout threshold, positive channel hysteresis VINP falling, VINN = –3.3V 120 mV
VUVLON(falling) Undervoltage lockout threshold,
negative channel		 VINN falling, VINP = 3.3V –3.1 –1.4 V
VUVLON(hys) Undervoltage lockout threshold, negative channel, hysteresis VINN rising, VINP = 3.3V 70 mV
VNR/SS Internal reference voltage 1.172 1.19 1.208 V
VFBP Positive feedback voltage 1.170 1.188 1.206 V
VFBN Negative feedback voltage –10 3.7 10 mV
VOUT Output voltage range(2) Positive channel VFBP 30 V
Negative channel –30 VFBN(1)
VOUTP accuracy VINP(nom) ≤ VINP ≤ 33V, 1mA ≤ IOUTP ≤ 150mA,
1.2V ≤ VOUTP(nom) ≤ 30V		 –1.5 1.5 %VOUT
VOUTN accuracy(3) –33V ≤ VINN ≤ VINN(nom), –150mA ≤ IOUTN ≤ –1mA, –30V ≤ VOUTN(nom) ≤ –1.2V –3 3 %VOUT
Negative VOUT channel accuracy –33V ≤ VINN ≤ VINN(nom) , –150mA ≤ IOUTN ≤ 1mA, –1.2 V < VOUTN(nom) < 0V –36 36 mV
–33V ≤ VINN ≤ VINN(nom) , –150mA ≤ IOUTN ≤ 1mA, VOUTN(nom) = 0V –12 12
ΔVOUT(ΔVIN) / VOUT(NOM) Line regulation, positive channel  VINP(nom) ≤ VINP ≤ 33V 0.035 %VOUT
Line regulation, negative channel –33V ≤ VINN ≤ VOUT(nom) + 1V 0.125
ΔVOUT(ΔIOUT) / VOUT(NOM) Load regulation, positive channel 1mA ≤ IOUTP ≤ 150mA –0.09 %VOUT
Load regulation, negative channel –150mA ≤ IOUTN ≤ –1mA 0.715
VDO Dropout voltage Positive channel IOUTP = 50mA, 3.3V ≤ VINP(nom) ≤ 33.0V,
VFBP = 1.070V		 175 300 mV
IOUTP = 150mA, 3.3V ≤ VINP(nom) ≤ 33.0V,
VFBP = 1.070V		 300 500
Negative channel IOUTN = –50mA, –3.3V ≤ VINN(nom) ≤ –33.0V,
VFBN = 0.0695V		 –250 –145
IOUTN = –150mA, –3.3V ≤ VINN(nom) ≤ –33.0V,
VFBN = 0.0695V		 –400 –275
VBUF Buffered reference output voltage VNR/SS V
VBUF/IBUF Buffered reference load regulation IBUF = 100µA to 1mA 1 mV/mA
VBUF – VNR/SS Output buffer offset voltage VNR/SS = 0.25V to 1.2V –4 3 8 mV
VOUTP–VOUTN DC output voltage difference with a forced REF voltage VNR/SS = 0.25V to 1.2V –10 10 %VNR/SS
ILIM Current limit Positive channel VOUTP = 90% VOUTP(nom) 200 330 500 mA
Negative channel VOUTN = 90% VOUTN(nom) –500 –300 –200
ISUPPLY Supply current Positive channel IOUTP = 0mA, R2N = open, VINP = 33V 75 150 µA
IOUTP = 150mA, R2N = open, VINP = 33V 904
Negative channel IOUTN = 0mA, VOUTN(nom)= 0V, R2N = open, VINN = –33V –150 –60
IOUTN = 150mA, R2N = open, VINN = –33V –1053
ISHDN Shutdown supply current Positive channel VEN = 0.4V, VINP = 33V 3.75 6.5 µA
Negative channel VEN = 0.4V, VINN = –33V –4.5 –2.25
IFBx Feedback pin leakage current Positive channel 5.5 100 nA
Negative channel –100 –9.7
INR/SS Soft-start charging current VNR/SS = 0.9V 3 5.1 6.7 µA
IEN Enable pin leakage current VEN = VINP = 33V 0.02 1 µA
VIH(EN) Enable high-level voltage 2.2 VINP V
VIL(EN) Enable low-level voltage 0 0.4 V
PSRR Power-supply rejection ratio |VIN| = 6V, |VOUT(nom)| = 5V, COUT = 10μF, CNR/SS = CFF= 10nF, f = 120Hz 69 dB
Vn Output noise voltage Positive channel VINP = 3.3V, VOUTP(nom) = VNR/SS, COUTP = 10μF, CNR/SS = 10nF, BW = 10Hz to 100kHz 20.63 µVRMS
VINP = 6V, VOUTP(nom) = 5V, COUTP = 10μF, CNR/SS = CFF = 10nF, BW = 10Hz to 100kHz 26.86
Negative channel VINN = –3V, VOUTN(nom) = –VNR/SS, COUTP = 10μF, CNR/SS = 10nF, BW = 10Hz to 100kHz 22.13
VINN = –6V, VOUTN(nom) = –5V, COUTP = 10μF, CNR/SS = CFF= 10nF, BW = 10Hz to 100kHz 28.68
RNR/SS Filter resistor from band gap to NR pin 350 kΩ
Tsd Thermal shutdown temperature Shutdown, temperature increasing 175 °C
Reset, temperature decreasing 160
(1) VOUT(target) = 0V, R1N = 10kΩ, R2N = open.
(2) To make sure VOUT does not drift up while the device is disabled, a minimum load current of 5µA is required.
(3) The device is not tested under conditions where the power dissipated across the device, PD, exceeds 2W.