SBVS336A September   2021  – May 2022 TPS7A94


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting and Regulation
      2. 7.3.2 Ultra-Low Noise and Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 7.3.3 Programmable Current Limit and Power-Good Threshold
      4. 7.3.4 Programmable Soft Start (NR/SS Pin)
      5. 7.3.5 Precision Enable and UVLO
      6. 7.3.6 Active Discharge
      7. 7.3.7 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
      4. 7.4.4 Current-Limit Operation
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Output Voltage Restart (Overshoot Prevention Circuit)
      2. 8.1.2  Precision Enable (External UVLO)
      3. 8.1.3  Undervoltage Lockout (UVLO) Operation
      4. 8.1.4  Dropout Voltage (VDO)
      5. 8.1.5  Power-Good Feedback (FB_PG Pin) and Power-Good Threshold (PG Pin)
      6. 8.1.6  Adjusting the Factory-Programmed Current Limit
      7. 8.1.7  Programmable Soft-Start and Noise-Reduction (NR/SS Pin)
      8. 8.1.8  Inrush Current
      9. 8.1.9  Optimizing Noise and PSRR
      10. 8.1.10 Adjustable Operation
      11. 8.1.11 Paralleling for Higher Output Current and Lower Noise
      12. 8.1.12 Recommended Capacitor Types
      13. 8.1.13 Load Transient Response
      14. 8.1.14 Power Dissipation (PD)
      15. 8.1.15 Estimating Junction Temperature
      16. 8.1.16 TPS7A94EVM-046 Thermal Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
      2. 10.1.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. Evaluation Modules
        2. Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DSC|10
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Programmable Soft-Start and Noise-Reduction (NR/SS Pin)

The NR/SS pin is the input to the inverting terminal of the error amplifier, see the Section 7.2. A resistor connected from this pin to GND sets the output voltage by the pin internal reference current INR/SS, VOUT = INR/SS × RNR/SS. Connecting a capacitor from this pin to GND significantly reduces the output noise, limits the input inrush-current, and soft-starts the output voltage. Use the minimum value or larger capacitor from NR/SS to ground as listed in the Section 6.5 table and place the NR/SS capacitor as close to the NR/SS and GND pins of the device as possible.

The device features a programmable, monotonic, voltage-controlled, soft-start circuit that is set to work with an external capacitor (CNR/SS). In addition to the soft-start feature, the CNR/SS capacitor also lowers the output voltage noise of the LDO. The soft-start feature can be used to eliminate power-up initialization problems. The controlled output voltage ramp also reduces peak inrush current during start up, minimizing start-up transients to the input power bus.

To achieve a monotonic start up, the device output voltage tracks the VNR/SS reference voltage until this reference reaches its set value (the set output voltage). The VNR/SS reference voltage is set by the RNR/SS resistor and, during start up, using a fast charging current (IFAST_SS) in addition to the INR/SS current, as shown in Figure 8-10, to charge the CNR/SS capacitor.

GUID-20210304-CA0I-JQ9G-RNNF-MXHTJGT7JRHC-low.gif Figure 8-10 Simplified Soft-Start Circuit

The 2.1-mA (typical) IFAST_SS current and 150 μA (typical) INR/SS current quickly charge CNR/SS until its voltage reaches approximately 93% of the set output voltage, then the IFAST_SS current disengages and only the INR/SS current continues to charge CNR/SS to its set output voltage level. If there is any error during start up or the output overshoot prevention circuit is triggered, the NR/SS discharge FET turns on, thus discharging the CNR/SS capacitor to protect both the LDO and the load.

The soft-start ramp time depends on the fast start-up (IFAST_SS) charging current, the reference current (INR/SS), CNR/SS capacitor value, and the set (targeted) output voltage (VOUT(target)). Equation 3 calculates the soft-start ramp time.

Equation 3. Soft-Start Time (tSS) = (VOUT(target) × CNR/SS) / (INR/SS + IFAST_SS)

The INR/SS current is provided in the Section 6.5 table and has a value of 150 μA (typical). The IFAST_SS current has a value of 2 mA (typical) for VIN > 2.5 V. Figure 8-11 and Figure 8-12 depict the INR/SS and IFAST_SS current versus VIN and temperature.

GUID-20220224-SS0I-KGNQ-RFH9-JMVGKVRZNRSX-low.pngFigure 8-11 INR/SS Reference vs Input Voltage and Temperature for VOUT = 3.3 V
GUID-20220224-SS0I-SH2H-B7CZ-CRKDJ9TPHDRC-low.pngFigure 8-12 IFAST_SS Reference vs Input Voltage and Temperature for VOUT = 3.3 V

Because the error amplifier is always operating in unity-gain configuration, the output voltage noise can only be adjusted by increasing the CNR/SS capacitor. The CNR/SS capacitor and RNR/SS resistor form a low-pass filter (LPF) that filters out the noise from the VNR/SS voltage reference, thereby reducing the device noise floor. The LPF is a single-pole filter and Equation 4 calculates the LPF cutoff frequency. Increasing the CNR/SS capacitor can significantly lower output voltage noise; however, doing so greatly lengthens start-up time. For low-noise applications, use a 4.7-μF CNR/SS for optimal noise and start-up time trade off.

Equation 4. Cutoff Frequency (fcutoff) = 1 / (2 × π × RNR/SS × CNR/SS)

The Section 6.6 section illustrates the impact of the CNR/SS capacitor on the LDO output voltage noise.