SBVS336A September 2021 – May 2022 TPS7A94
Achieving higher output current and lower noise is achievable by paralleling two or more LDOs. Implementation must be carefully planned out to optimize performance and minimize output current imbalance.
Because the TPS7A94 output voltage is set by a resistor driven by a current source, the NR/SS resistor and capacitor must be adjusted as per the following:
When connecting the input and NR/SS pin together, and with the LDO being a buffer, the current imbalance is only affected by the error offset voltage of the error amplifier. As such, the current imbalance can be expressed as:
With the typical offset voltage of 200 μV, considering no error from the design of the PCB ballast resistor (ΔRBALLAST = 0) and a 100-mA maximum current imbalance, the ballast resistor must be 4 mΩ or greater; see Figure 8-16.
Using the configuration described, the LDO output noise is reduced by:
In Figure 8-16, the noise is reduced by 1 / √2.