SBVS336A September   2021  – May 2022 TPS7A94

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting and Regulation
      2. 7.3.2 Ultra-Low Noise and Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 7.3.3 Programmable Current Limit and Power-Good Threshold
      4. 7.3.4 Programmable Soft Start (NR/SS Pin)
      5. 7.3.5 Precision Enable and UVLO
      6. 7.3.6 Active Discharge
      7. 7.3.7 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
      4. 7.4.4 Current-Limit Operation
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Output Voltage Restart (Overshoot Prevention Circuit)
      2. 8.1.2  Precision Enable (External UVLO)
      3. 8.1.3  Undervoltage Lockout (UVLO) Operation
      4. 8.1.4  Dropout Voltage (VDO)
      5. 8.1.5  Power-Good Feedback (FB_PG Pin) and Power-Good Threshold (PG Pin)
      6. 8.1.6  Adjusting the Factory-Programmed Current Limit
      7. 8.1.7  Programmable Soft-Start and Noise-Reduction (NR/SS Pin)
      8. 8.1.8  Inrush Current
      9. 8.1.9  Optimizing Noise and PSRR
      10. 8.1.10 Adjustable Operation
      11. 8.1.11 Paralleling for Higher Output Current and Lower Noise
      12. 8.1.12 Recommended Capacitor Types
      13. 8.1.13 Load Transient Response
      14. 8.1.14 Power Dissipation (PD)
      15. 8.1.15 Estimating Junction Temperature
      16. 8.1.16 TPS7A94EVM-046 Thermal Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
      2. 10.1.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DSC|10
Thermal pad, mechanical data (Package|Pins)
Orderable Information

TPS7A94EVM-046 Thermal Analysis

The TPS7A94EVM-046 EVM was used to develop the TPS7A9401DRC thermal model. The DRC package is a 3-mm × 3-mm, 10-pin VQFN with 25-µm plating on each via. The EVM is a 2.85-inch × 3.35-inch (72.39 mm × 85.09 mm) PCB comprised of four layers. Table 8-5 lists the layer stackup for the EVM. Figure 8-18 to Figure 8-22 illustrate the various layer details for the EVM.

Table 8-5 TPS7A94EVM-046 PCB Stackup
LAYER NAME MATERIAL THICKNESS (mil)
1 Top overlay
2 Top solder Solder resist 0.4
3 Top layer Copper 2.8
4 Dielectric 1 FR-4 high Tg 10
5 Mid layer 1 Copper 2.8
6 Dielectric 2 FR-4 high Tg 30
7 Mid layer 2 Copper 2.8
8 Dielectric 3 FR-4 high Tg 10
9 Bottom layer Copper 2.8
10 Bottom solder Solder resist 0.4
Figure 8-18 Top Composite View
Figure 8-20 Mid Layer 1 Routing
Figure 8-22 Bottom Layer Routing
Figure 8-19 Top Layer Routing
Figure 8-21 Mid Layer 2 Routing

Figure 8-23 to Figure 8-25 show the thermal gradient on the PCB and device that results when a 1-W power dissipation is used through the pass transistor with a 25°C ambient temperature. Table 8-6 shows thermal simulation data for the TPS7A94EVM-046.

Table 8-6 TPS7A94EVM-046 Thermal Simulation Data
DUT RθJA (°C/W) JB (°C/W) JT (°C/W)
TPS7A94EVM-046 25.6 11.5 0.3
GUID-20210513-CA0I-QWGS-8QHJ-CFBNWRFZ7JTK-low.png
 
Figure 8-23 TPS7A94EVM-046 3D View
GUID-20210513-CA0I-78DD-M3HQ-WGZB2NLTP1XL-low.pngFigure 8-25 TPS7A94EVM-046 Device Thermal Gradient
GUID-20210513-CA0I-NSWC-Z5TJ-JBW9HZWD9WFS-low.pngFigure 8-24 TPS7A94EVM-046 PCB Thermal Gradient