SBVS336A September   2021  – May 2022 TPS7A94


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting and Regulation
      2. 7.3.2 Ultra-Low Noise and Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 7.3.3 Programmable Current Limit and Power-Good Threshold
      4. 7.3.4 Programmable Soft Start (NR/SS Pin)
      5. 7.3.5 Precision Enable and UVLO
      6. 7.3.6 Active Discharge
      7. 7.3.7 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
      4. 7.4.4 Current-Limit Operation
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Output Voltage Restart (Overshoot Prevention Circuit)
      2. 8.1.2  Precision Enable (External UVLO)
      3. 8.1.3  Undervoltage Lockout (UVLO) Operation
      4. 8.1.4  Dropout Voltage (VDO)
      5. 8.1.5  Power-Good Feedback (FB_PG Pin) and Power-Good Threshold (PG Pin)
      6. 8.1.6  Adjusting the Factory-Programmed Current Limit
      7. 8.1.7  Programmable Soft-Start and Noise-Reduction (NR/SS Pin)
      8. 8.1.8  Inrush Current
      9. 8.1.9  Optimizing Noise and PSRR
      10. 8.1.10 Adjustable Operation
      11. 8.1.11 Paralleling for Higher Output Current and Lower Noise
      12. 8.1.12 Recommended Capacitor Types
      13. 8.1.13 Load Transient Response
      14. 8.1.14 Power Dissipation (PD)
      15. 8.1.15 Estimating Junction Temperature
      16. 8.1.16 TPS7A94EVM-046 Thermal Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
      2. 10.1.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. Evaluation Modules
        2. Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DSC|10
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Power-Good Feedback (FB_PG Pin) and Power-Good Threshold (PG Pin)

For proper device operation, the resistor divider network input to the FB_PG pin must be connected. The FB_PG pin must not be left floating because this pin represents an analog input to the device internal logic and its input impedance is sampled during device start up.

The PG pin is an output indicating whether the LDO is ready to provide power. This pin is implemented using an open-drain architecture. The FB_PG pin is used to program the PG pin and serves a dual purpose of programming the PG threshold assert voltage and adjusting the current limit, ICL.

The PG pin must use the minimum value or larger pullup resistor from PG to IN, see Figure 8-8, or the external rail as listed in the Section 6.5 table. If PG functionality is not used, leave this pin floating or connected to GND.

The FB_PG pin uses the parallel impedance formed by the resistor divider RFB_PG(TOP)­ and RFB_PG(BOTTOM) to program the current limit value during LDO initialization. If this impedance is less than 10 kΩ, then the nominal factory-programmed, current-limit value is selected. If the input impedance is less than 50 kΩ, but greater than 10 kΩ, then 80% of the nominal factory-programmed current limit is selected. If the input impedance is less than 100 kΩ, but greater than 50 kΩ, then 60% of the nominal factory-programmed current limit is selected. Connect the RFB_PG(TOP) and RFB_PG(BOTTOM) resistors as indicated in this section for proper operation of the LDO. Do not float this pin.

When initialization is complete, the voltage divider provides the necessary feedback to the PG pin by setting the PG assert threshold voltage.

To properly select the values of the RFB_PG(TOP) and RFB_PG(BOTTOM) resistors, see the Section 8.1.6 section for detailed explanation and calculation.


The RFB_PG(TOP) and RFB_PG(BOTTOM) resistor divider ratio is used to set the power-good assert threshold voltage between 85% to 95% of the VFB_PG voltage for 60% and 80% of the nominal factory-programmed current limit.

If the current limit is set for 100% of the nominal factory-programmed current limit, the PG threshold range is not limited. A PG threshold greater than 80% is common for system where startup inrush current needs to be minimized. Lower PG threshold may be needed in system with fast startup time constraints.

Setting the PG threshold based off the VFB_PG voltage sets the PG to assert when the output voltage reaches the corresponding percentage level of VFB_PG because VFB_PG is a scaled version of the output voltage. Figure 8-8 shows the internal circuitry for both the FB_PG and PG pins.

GUID-20210430-CA0I-XMVN-9DTP-1XVJKSJNMZ2W-low.gif Figure 8-8 Programmable Power-Good Threshold Simplified Schematic

The PG pin pullup resistor value must be between 10 kΩ and 100 kΩ. The lower limit of 10 kΩ results from the maximum pulldown strength of the power-good transistor, and the upper limit of 100 kΩ results from the maximum leakage current at the power-good node. If the pullup resistor is outside of this range, then the power-good signal may not read a valid digital logic level.

The state of the PG signal is only valid when the FB_PG pin resistor divider network is set properly and the device is in normal operating mode.