SLVSJH7 October   2025 TPS7E67-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Enable (EN)
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Power-Good (PG)
      4. 6.3.4 Adjustable Power-Good Delay Timer (DELAY)
      5. 6.3.5 Undervoltage Lockout
      6. 6.3.6 Thermal Shutdown
      7. 6.3.7 Foldback Current Limit
      8. 6.3.8 Power Limit
      9. 6.3.9 Output Pulldown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Functional Mode Comparison
      2. 6.4.2 Normal Operation
      3. 6.4.3 Dropout Operation
      4. 6.4.4 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjustable Device Feedback Resistor Selection
      2. 7.1.2 Recommended Capacitor Types
      3. 7.1.3 Input and Output Capacitor Selection
      4. 7.1.4 Reverse Current
      5. 7.1.5 Feed-Forward Capacitor
      6. 7.1.6 Dropout Voltage
      7. 7.1.7 Estimating Junction Temperature
      8. 7.1.8 Power Dissipation (PD)
      9. 7.1.9 Power Dissipation Versus Ambient Temperature
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Choose Feedback Resistors
      3. 7.2.3 Setting the Adjustable Power-Good Delay
      4. 7.2.4 Power Supply Recommendations
      5. 7.2.5 Layout
        1. 7.2.5.1 Layout Guidelines
        2. 7.2.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2 Choose Feedback Resistors

For this design example, VOUT is set to 3.3V. The following equations set the feedback divider resistors for the desired output voltage:

Equation 15. VOUT = VFB × (1 + R1 / R2)
Equation 16. R1 + R2 ≤ VOUT / (IFB × 100)

For improved output accuracy, use Equation 16 and IFB = 10nA as listed in the Section 5.5 table to calculate the upper limit for series feedback resistance (R1 + R2 ≤ 3.3MΩ).

The control-loop error amplifier drives the FB pin to the same voltage as the internal reference (VFB = 1.2V, as listed in the Section 5.5 table). Use Equation 15 to determine the ratio of R1 / R2 = 1.75 Use this ratio and solve Equation 16 for R1. Now calculate the upper limit for R1 ≤ 2.1MΩ. Select a standard value resistor for R1 = 1.75MΩ.

Reference Equation 17 and solve for R2:

Equation 17. R2 = R1 / [(VOUT / VFB) – 1]

From Equation 17, R2 = 1MΩ is determined. Select a standard value resistor for R2 = 1MΩ. VOUT = 3.3V. Verify that the feedback divider current is greater than the minimum value in the Section 5.3 table.

The following equation calculates the feedback divider current.

Equation 18. IFB_Divider = VOUT / (R1 + R2)