SLUSCV6A April 2017 – February 2018 UCC21225A
Channel 1 (Indigo): UCC21225A INA pin signal.
Channel 2 (Cyan): UCC21225A INB pin signal.
Channel 3 (Magenta): Gate-source signal on the high side power transistor.
Channel 4 (Green): Gate-source signal on the low side power transistor.
In Figure 39, INA and INB are sent complimentary 3.3-V, 20%/80% duty-cycle signals. The gate drive signals on the power transistor have a 250-ns dead time, shown in the measurement section of Figure 39. The dead time matching is approximately 10-ns with the 250-ns dead-time setting. Note that with high voltage present, lower bandwidth differential probes are required, which limits the achievable accuracy of the measurement.
Figure 40 shows a zoomed-in version of the waveform of Figure 39, with measurements for propagation delay and rising/falling time. Importantly, the output waveform is measured between the power transistors’ gate and source pins, and is not measured directly from the driver OUTA and OUTB pins. Due to the split on and off resistors (Ron, Roff), different sink and source currents, and the Miller plateau, different rising (60, 120 ns) and falling time (25 ns) are observed in Figure 40.