SLUSCV6A April 2017 – February 2018 UCC21225A
Figure 41 shows a 2-layer PCB layout example with the signals and key components labeled.
There are no PCB traces or copper between the primary and secondary side, which ensures isolation performance.
PCB trace spacing between the high-side and low-side gate drivers in the output stage are increased to minimize cross-talk due to parasitic capacitance coupling between the switching node VSSA (SW), where high dv/dt may exist, and the low-side gate drive circuit.
The location of the PCB cutout between the primary side and secondary sides, which ensures isolation performance.