SLUSCV6A April 2017 – February 2018 UCC21225A
The external gate driver resistors, RON/ROFF, are used to:
As mentioned in Output Stage, the UCC21225A has a pull-up structure with a P-channel MOSFET and an additional pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A. Therefore, the peak source current can be predicted with:
In this example:
Therefore, the high-side and low-side peak source currents are 2.2 A and 2.5 A respectively. Similarly, the peak sink current can be calculated with:
In this example,
Therefore, the high-side and low-side peak sink currents are 5.1 A and 5.5 A respectively.
Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and undershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (CISS) of the power transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close to the parasitic ringing period.