SLUSD49A September   2017  – January 2019 UCC256303


  1. Features
  2. Applications
  3. Description
    1.     Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Hybrid Hysteretic Control
      2. 7.3.2  Regulated 12-V Supply
      3. 7.3.3  Feedback Chain
      4. 7.3.4  Optocoupler Feedback Signal Input and Bias
      5. 7.3.5  System External Shut Down
      6. 7.3.6  Pick Lower Block and Soft Start Multiplexer
      7. 7.3.7  Pick Higher Block and Burst Mode Multiplexer
      8. 7.3.8  VCR Comparators
      9. 7.3.9  Resonant Capacitor Voltage Sensing
      10. 7.3.10 Resonant Current Sensing
      11. 7.3.11 Bulk Voltage Sensing
      12. 7.3.12 Output Voltage Sensing
      13. 7.3.13 High Voltage Gate Driver
      14. 7.3.14 Protections
        1. ZCS Region Prevention
        2. Over Current Protection (OCP)
        3. Over Output Voltage Protection (VOUTOVP)
        4. Over Input Voltage Protection (VINOVP)
        5. Under Input Voltage Protection (VINUVP)
        6. Boot UVLO
        7. RVCC UVLO
        8. Over Temperature Protection (OTP)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Burst Mode Control
      2. 7.4.2 Soft-Start and Burst-Mode Threshold
      3. 7.4.3 System States and Faults State Machine
      4. 7.4.4 Waveform Generator State Machine
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  LLC Power Stage Requirements
        2.  LLC Gain Range
        3.  Select Ln and Qe
        4.  Determine Equivalent Load Resistance
        5.  Determine Component Parameters for LLC Resonant Circuit
        6.  LLC Primary-Side Currents
        7.  LLC Secondary-Side Currents
        8.  LLC Transformer
        9.  LLC Resonant Inductor
        10. LLC Resonant Capacitor
        11. LLC Primary-Side MOSFETs
        12. Design Considerations for Adaptive Dead-Time
        13. LLC Rectifier Diodes
        14. LLC Output Capacitors
        15. BLK Pin Voltage Divider
        16. BW Pin Voltage Divider
        17. ISNS Pin Differentiator
        18. VCR Pin Capacitor Divider
        19. Burst Mode Programming
        20. Soft-Start Capacitor
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 VCC Pin Capacitor
    2. 9.2 Boot Capacitor
    3. 9.3 RVCC Pin Capacitor
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support (if applicable)
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DDB|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Burst Mode Programming

The burst mode programming interface enables user to program a burst mode threshold voltage (VLL) which adaptively changes with input voltage. This way, consistent burst threshold can be achieved across VIN range, thus making the efficiency curve more consistent across VIN range.

The following relationship exists between VLL voltage and BLK pin voltage:

Equation 68. UCC256303 qu68_sluscu6.gif

In this equation, VLL is the burst mode threshold voltage; VBLK is BLK pin voltage; two parameters a and b can be programmed by two external resistors.

After soft start is done, the sensed BLK pin voltage is applied to LL/SS pin from inside the IC through a buffer. As shown in the figure below, this creates a difference between the current flowing through the programming resistor RLLUpper and RLLLower. The difference between the current flows into the LL/SS pin, mirrored and then applied to a 250-kΩ resistor RLL. The voltage on RLL is used as VLL.

UCC256303 fig55_sluscu6.gifFigure 44. Burst Mode Programming

The relationship between VLL and VBLK can then be derived:

Equation 69. UCC256303 qu69_sluscu6.gif

Equation 69 rearranged produces Equation 70

Equation 70. UCC256303 qu70_sluscu6.gif

To determine RLLUpper and RLLLower, two sets of (VLL, VBLK) values are required. VBLK can be measured directly from BLK pin. VLL level can be measured by inserting a 10-kΩ resistor between the feedback optocoupler emitter and ground. Assume the voltage measured on the 10-kΩ resistor is V10k. Then VLL voltage can be calculated as:

Equation 71. UCC256303 qu71_sluscu6.gif

Remove the RLLUpper. In this way, the VLL voltage is at its minimal value 0.7 V, which is determined by the internal circuit design. Then adjust the load current to the desired burst mode threshold load level, and make sure the power stage does not burst in this condition. For example, 10% load is the desired burst mode threshold level. With 10 A as the full-load condition, set the load current to 1 A. After the load current is set, change the input voltage to two different voltages and record two different readings (V10k, VBLK). Then based on Equation 70 and Equation 71, RLLUpper and RLLLower can be solved.

In this example select the lower resistor to be 402 kΩ and the upper resistor to be 732 kΩ.