SLUSD49A September   2017  – January 2019

PRODUCTION DATA.

1. Features
2. Applications
3. Description
4. Revision History
5. Pin Configuration and Functions
6. Specifications
7. Detailed Description
1. 7.1 Overview
2. 7.2 Functional Block Diagram
3. 7.3 Feature Description
4. 7.4 Device Functional Modes
8. Application and Implementation
1. 8.1 Application Information
2. 8.2 Typical Application
1. 8.2.1 Design Requirements
2. 8.2.2 Detailed Design Procedure
3. 8.2.3 Application Curves
9. Power Supply Recommendations
10. 10Layout
11. 11Device and Documentation Support
1. 11.1 Device Support
1. 11.1.1 Development Support
2. 11.2 Documentation Support (if applicable)
4. 11.4 Community Resources
6. 11.6 Electrostatic Discharge Caution
7. 11.7 Glossary
12. 12Mechanical, Packaging, and Orderable Information

#### Package Options

Refer to the PDF data sheet for device specific package drawings

• DDB|14

#### 8.2.2.19 Burst Mode Programming

The burst mode programming interface enables user to program a burst mode threshold voltage (VLL) which adaptively changes with input voltage. This way, consistent burst threshold can be achieved across VIN range, thus making the efficiency curve more consistent across VIN range.

The following relationship exists between VLL voltage and BLK pin voltage:

Equation 68.

In this equation, VLL is the burst mode threshold voltage; VBLK is BLK pin voltage; two parameters a and b can be programmed by two external resistors.

After soft start is done, the sensed BLK pin voltage is applied to LL/SS pin from inside the IC through a buffer. As shown in the figure below, this creates a difference between the current flowing through the programming resistor RLLUpper and RLLLower. The difference between the current flows into the LL/SS pin, mirrored and then applied to a 250-kΩ resistor RLL. The voltage on RLL is used as VLL.

The relationship between VLL and VBLK can then be derived:

Equation 69.

Equation 69 rearranged produces Equation 70

Equation 70.

To determine RLLUpper and RLLLower, two sets of (VLL, VBLK) values are required. VBLK can be measured directly from BLK pin. VLL level can be measured by inserting a 10-kΩ resistor between the feedback optocoupler emitter and ground. Assume the voltage measured on the 10-kΩ resistor is V10k. Then VLL voltage can be calculated as:

Equation 71.

Remove the RLLUpper. In this way, the VLL voltage is at its minimal value 0.7 V, which is determined by the internal circuit design. Then adjust the load current to the desired burst mode threshold load level, and make sure the power stage does not burst in this condition. For example, 10% load is the desired burst mode threshold level. With 10 A as the full-load condition, set the load current to 1 A. After the load current is set, change the input voltage to two different voltages and record two different readings (V10k, VBLK). Then based on Equation 70 and Equation 71, RLLUpper and RLLLower can be solved.

In this example select the lower resistor to be 402 kΩ and the upper resistor to be 732 kΩ.