SLUS157Q December   1999  – October 2019 UCC1895 , UCC2895 , UCC3895


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Application Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  ADS (Adaptive Delay Set)
      2. 7.3.2  CS (Current Sense)
      3. 7.3.3  CT (Oscillator Timing Capacitor)
      4. 7.3.4  DELAB and DELCD (Delay Programming Between Complementary Outputs)
      5. 7.3.5  EAOUT, EAP, and EAN (Error Amplifier)
      6. 7.3.6  OUTA, OUTB, OUTC, and OUTD (Output MOSFET Drivers)
      7. 7.3.7  PGND (Power Ground)
      8. 7.3.8  RAMP (Inverting Input of the PWM Comparator)
      9. 7.3.9  REF (Voltage Reference)
      10. 7.3.10 RT (Oscillator Timing Resistor)
      11. 7.3.11 GND (Analog Ground)
      12. 7.3.12 SS/DISB (Soft Start/Disable)
      13. 7.3.13 SYNC (Oscillator Synchronization)
      14. 7.3.14 VDD (Chip Supply)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Programming DELAB, DELCD and the Adaptive Delay Set
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Power Loss Budget
        2.  Preliminary Transformer Calculations (T1)
        3.  QA, QB, QC, QD FET Selection
        4.  Selecting LS
        5.  Selecting Diodes DB and DC
        6.  Output Inductor Selection (LOUT)
        7.  Output Capacitance (COUT)
        8.  Select Rectifier Diodes
        9.  Input Capacitance (CIN)
        10. Current Sense Network (CT, RCS, RR, DA)
          1. Output Voltage Setpoint
          2. Voltage Loop Compensation
          3. Setting the Switching Frequency
          4. Soft Start
          5. Setting the Switching Delays
          6. Setting the Slope Compensation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resource
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Programming DELAB, DELCD and the Adaptive Delay Set

The UCC3895 allows the user to set the delay between switch commands within each leg of the full-bridge power circuit according to Equation 5.

Equation 5. UCC1895 UCC2895 UCC3895 eq_5_slus157.gif

From Equation 5 VDEL is determined in conjunction with the desire to use (or not) the ADS feature from Equation 6.

Equation 6. UCC1895 UCC2895 UCC3895 eq_6_slus157.gif

Figure 14 illustrates the resistors needed to program the delay periods and the ADS function.

UCC1895 UCC2895 UCC3895 ai_prog_delay_slus157.gifFigure 14. Programming Adaptive Delay Set

The ADS allows the user to vary the delay times between switch commands within each of the two legs of the converter. The delay-time modulation is implemented by connecting ADS (pin 11) to CS, GND, or a resistive divider from CS through ADS to GND to set VADS as shown in Figure 14. From Equation 6 for VDEL, if ADS is tied to GND then VDEL rises in direct proportion to VCS, causing a decrease in tDELAY as the load increases. In this condition, the maximum value of VDEL is 2 V.

If ADS is connected to a resistive divider between CS and GND, the term (VCS – VADS) becomes smaller, reducing the level of VDEL. This reduction decreases the amount of delay modulation. In the limit of ADS tied to CS, VDEL = 0.5 V and no delay modulation occurs. Figure 15 graphically shows the delay time versus load for varying adaptive delay set feature voltages (VADS).

In the case of maximum delay modulation (ADS = GND), when the circuit goes from light load to heavy load, the variation of VDEL is from 0.5 to 2 V. This change causes the delay times to vary by a 4:1 ratio as the load is changed.

The ability to program an adaptive delay is a desirable feature because the optimum delay time is a function of the current flowing in the primary winding of the transformer, and changes by a factor of 10:1 or more as circuit loading changes. Reference 7 (see the Related Documentation section) describes the many interrelated factors for choosing the optimum delay times for the most efficient power conversion, and illustrates an external circuit to enable ADS using the UC3879. Implementing this adaptive feature is simplified in the UCC3895 controller, giving the user the ability to tailor the delay times to suit a particular application with a minimum of external parts.

UCC1895 UCC2895 UCC3895 ai_td_varying_slus157.gifFigure 15. Delay Time Under Varying ADS Voltages
UCC1895 UCC2895 UCC3895 td3_slus157.gif
No Output Delay Shown, COMP to RAMP offset not included.
Figure 16. UCC3895 Timing Diagram