SLUS157Q December   1999  – October 2019 UCC1895 , UCC2895 , UCC3895


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Application Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  ADS (Adaptive Delay Set)
      2. 7.3.2  CS (Current Sense)
      3. 7.3.3  CT (Oscillator Timing Capacitor)
      4. 7.3.4  DELAB and DELCD (Delay Programming Between Complementary Outputs)
      5. 7.3.5  EAOUT, EAP, and EAN (Error Amplifier)
      6. 7.3.6  OUTA, OUTB, OUTC, and OUTD (Output MOSFET Drivers)
      7. 7.3.7  PGND (Power Ground)
      8. 7.3.8  RAMP (Inverting Input of the PWM Comparator)
      9. 7.3.9  REF (Voltage Reference)
      10. 7.3.10 RT (Oscillator Timing Resistor)
      11. 7.3.11 GND (Analog Ground)
      12. 7.3.12 SS/DISB (Soft Start/Disable)
      13. 7.3.13 SYNC (Oscillator Synchronization)
      14. 7.3.14 VDD (Chip Supply)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Programming DELAB, DELCD and the Adaptive Delay Set
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Power Loss Budget
        2.  Preliminary Transformer Calculations (T1)
        3.  QA, QB, QC, QD FET Selection
        4.  Selecting LS
        5.  Selecting Diodes DB and DC
        6.  Output Inductor Selection (LOUT)
        7.  Output Capacitance (COUT)
        8.  Select Rectifier Diodes
        9.  Input Capacitance (CIN)
        10. Current Sense Network (CT, RCS, RR, DA)
          1. Output Voltage Setpoint
          2. Voltage Loop Compensation
          3. Setting the Switching Frequency
          4. Soft Start
          5. Setting the Switching Delays
          6. Setting the Slope Compensation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resource
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Voltage Loop Compensation

We choose a standard configuration for a TL431 / optocoupler based feedback network. Type 2 loop compensation is appropriate for a design using peak current mode control. First we set the DC operating points for the TL431 (U1) and the optocoupler (U2).

We assume that the optocoupler (U2) has a current transfer ratio (CTR) of 1 and choose to operate it at a maximum LED current, IF of 10 mA. RD is then given by:

Equation 103. UCC1895 UCC2895 UCC3895 qu_q_103_lus157.gif

We set the parallel combination of RG and RF to 2.4 kΩ for a nominal 10-dB gain for output perturbations via the direct path from RD to the optocoupler diode. This path exists in parallel with the path through RA and the TL431. The direct path is important at frequencies where the gain of the TL431 integrator has fallen to 0 dB.

RG and RF form a potential divider whose function is to keep the EAP pin within the upper limit of its common mode input range (VCM_MAX = 3.6 V) when there is no current in the photo-transistor. RG is connected to VREF and this constraint on the voltage at the EAP pin gives:

Equation 104. UCC1895 UCC2895 UCC3895 qu_q_104_lus157.gif

Since we know the parallel value of RF and RG and their ratio (RF/RG), we calculate RF as follows:

Equation 105. UCC1895 UCC2895 UCC3895 qu_q_105_lus157.gif


Equation 106. UCC1895 UCC2895 UCC3895 qu_q_106_lus157.gif

At low frequencies the gain is dominated by the response of the TL431 error amplifier which is configured as a pure integrator. The TL431 has a typical open loop gain of about 60 dB at DC, which decreases at the normal –20 dB per decade. Its gain will be 0 dB when the impedance of CE falls to that of RA. Even though the TL431 gain has fallen to 0 dB, the system still has 10-dB gain due to the direct path through RD.

We put the zero due to capacitor CE and resistor RA at the desired 0-dB gain frequency of 2 kHz. Since RA is already selected from VOUT setpoint considerations we calculate CE as follows:

Equation 107. UCC1895 UCC2895 UCC3895 qu_q_107_lus157.gif

The optocoupler has a 10-dB response through the direct path, to perturbations on VOUT. At higher frequencies the capacitance at the collector of the optocoupler (CF) forms a pole with the resistor in series with the optocoupler LED. The gain then rolls off in half a decade to reach 0 dB. With CF = 68 nF this pole is at about 2.8 kHz.

Having chosen the component values in the feedback path around the TL431 we can draw a Bode Plot of the VOUT to EAP transfer function GC(f).

The control to output transfer function of the power train is approximated by:

Equation 108. UCC1895 UCC2895 UCC3895 qu_q_108_lus157.gif


  • s = 2πjf is the complex frequency
  • sPP is FSW / 2 = 50 kHz in this case
  • The overall loop response is then given by GC(f). GC(o).

This loop response has a crossover frequency of 7.5 kHz. TI recommends that you check the loop stability of the final design with load transient tests and by checking that the gain and phase margins are sufficient. RLOOP provides a convenient point to inject signals for loop gain and phase measurements. The feedback network may need to be adjusted to achieve satisfactory performance.