SLUSB72D March 2013 – April 2021 UCD3138064
UCD3138 and UCD3138064 need a 2.2-µF pullup capacitor from BP18 to V33 as described before. Capacitors with a value of 2.2 µF and 1 µF create a capacitor divider which pull BP18 up as V33 rises. Ensure that as V33 rises, the slew rate is not fast enough to cause BP18 to overshoot, resulting in a reliability issue. TI requires that the maximum voltage of BP18 does not exceed 1.95 V. By calculation, if V33 ramps up linearly, the maximum V33 slew rate should be less than 6 V/ms.
Also, the internal BP18 regulator is enabled when V33 is higher than VGH and POR is activated. V33 charges the capacitor of BP18 through the internal regulator. This charge causes a voltage dip in the V33 pin as shown in Figure 11-1, and the charge may trigger a V33 undervoltage (POR) event, causing a chip reset. To prevent POR trigger signal oscillation and successive chip resets, TI recommends a minimum slew rate of 2.6 V/ms.
From the Figure 11-1 recommendations, the slew rate using the 2.2 uF/1uF capacitor combination requires that the slew rate must be as follows: