SLUSB72D March   2013  – April 2021 UCD3138064

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Options
    1. 6.1 Device Comparison Table
    2. 6.2 Product Selection Matrix
  7. 7 Pin Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings (1)
    2. 8.2  Handling Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Timing Characteristics
    7. 8.7  PMBus/SMBus/I2C Timing
    8. 8.8  Power On Reset (POR) / Brown Out Reset (BOR)
    9. 8.9  Typical Clock Gating Power Savings
    10. 8.10 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 ARM Processor
      2. 9.1.2 Memory
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  System Module
        1. 9.3.1.1 Address Decoder (DEC)
        2. 9.3.1.2 Memory Management Controller (MMC)
        3. 9.3.1.3 System Management (SYS)
        4. 9.3.1.4 Central Interrupt Module (CIM)
      2. 9.3.2  Peripherals
        1. 9.3.2.1 Digital Power Peripherals
          1. 9.3.2.1.1 Front End
          2. 9.3.2.1.2 DPWM Module
          3. 9.3.2.1.3 DPWM Events
          4. 9.3.2.1.4 High Resolution DPWM
          5. 9.3.2.1.5 Over Sampling
          6. 9.3.2.1.6 DPWM Interrupt Generation
          7. 9.3.2.1.7 DPWM Interrupt Scaling/Range
      3. 9.3.3  Automatic Mode Switching
        1. 9.3.3.1 Phase Shifted Full Bridge Example
        2. 9.3.3.2 LLC Example
        3. 9.3.3.3 Mechanism For Automatic Mode Switching
      4. 9.3.4  DPWMC, Edge Generation, Intramux
      5. 9.3.5  Filter
        1. 9.3.5.1 Loop Multiplexer
        2. 9.3.5.2 Fault Multiplexer
      6. 9.3.6  Communication Ports
        1. 9.3.6.1 SCI (UART) Serial Communication Interface
        2. 9.3.6.2 PMBUS/I2C
        3. 9.3.6.3 SPI
      7. 9.3.7  Real Time Clock
      8. 9.3.8  Timers
        1. 9.3.8.1 24-Bit Timer
        2. 9.3.8.2 16-Bit PWM Timers
        3. 9.3.8.3 Watchdog Timer
      9. 9.3.9  General Purpose ADC12
      10. 9.3.10 Miscellaneous Analog
      11. 9.3.11 Brownout
      12. 9.3.12 Global I/O
      13. 9.3.13 Temperature Sensor Control
      14. 9.3.14 I/O Mux Control
      15. 9.3.15 Current Sharing Control
      16. 9.3.16 Temperature Reference
    4. 9.4 Device Functional Modes
      1. 9.4.1 DPWM Modes Of Operation
        1. 9.4.1.1 Normal Mode
        2. 9.4.1.2 Phase Shifting
        3. 9.4.1.3 DPWM Multiple Output Mode
        4. 9.4.1.4 DPWM Resonant Mode
      2. 9.4.2 Triangular Mode
      3. 9.4.3 Leading Edge Mode
    5. 9.5 Memory
      1. 9.5.1 Register Maps
        1. 9.5.1.1 CPU Memory Map and Interrupts
          1. 9.5.1.1.1 Memory Map (After Reset Operation)
          2. 9.5.1.1.2 Memory Map (Normal Operation)
          3. 9.5.1.1.3 Memory Map (System and Peripherals Blocks)
        2. 9.5.1.2 Boot ROM
        3. 9.5.1.3 Customer Boot Program
        4. 9.5.1.4 Flash Management
        5. 9.5.1.5 Synchronous Rectifier MOSFET Ramp and IDE Calculation
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration Overview
        2. 10.2.2.2 DPWM Initialization for PSFB
          1. 10.2.2.2.1 DPWM Synchronization
        3. 10.2.2.3 Fixed Signals to Bridge
        4. 10.2.2.4 Dynamic Signals to Bridge
        5. 10.2.2.5 System Initialization for PCM
          1. 10.2.2.5.1 Use of Front Ends and Filters in PSFB
          2. 10.2.2.5.2 Peak Current Detection
          3. 10.2.2.5.3 Peak Current Mode (PCM)
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Introduction To Power Supply and Layout Recommendations
    2. 11.2 3.3-V Supply Pins
    3. 11.3 Recommendation for V33 Ramp up Slew Rate for UCD3138 and UCD3138064
    4. 11.4 Recommendation for RC Time Constant of RESET Pin for UCD3138 and UCD3138064
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 EMI and EMC Mitigation Guidelines
      2. 12.1.2 BP18 Pin
      3. 12.1.3 Additional Bias Guidelines
      4. 12.1.4 UART Communication Port
    2. 12.2 Layout Example
      1. 12.2.1 UCD3138 and UCD3138064 40 Pin
      2. 12.2.2 UCD3138 and UCD3138064 64 Pin
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5 Electrical Characteristics

V33A = V33D = V33DIO = 3.3 V; 1μF from BP18 to DGND, TJ = –40 °C to 125 °C (unless otherwise noted)
PARAMETERTEST CONDITIONMINTYPMAXUNIT
SUPPLY CURRENT
I33AMeasured on V33A. The device is powered up but all ADC12 and EADC sampling is disabled6.3mA
I33DIOAll GPIO and communication pins are open0.35mA
I33DROM program execution60mA
I33D (5)Flash programming in ROM mode70mA
I33The device is in ROM mode with all DPWMs enabled and switching at 2 MHz. The DPWMs are all unloaded.100mA
ERROR ADC INPUTS EAP, EAN
EAP – AGND–0.151.998V
EAP – EAN–0.2561.848V
Typical error rangeAFE = 0–256248mV
EAP – EAN Error voltage digital resolutionAFE = 30.811.20mV
AFE = 21.722.30mV
AFE = 13.5544.45mV
AFE = 06.9089.10mV
REAInput impedance (See Figure 9-1)AGND reference0.5MΩ
IOFFSETInput offset current (See Figure 9-1)–55μA
EADC OffsetInput voltage = 0 V at AFE = 0–22LSB
Input voltage = 0 V at AFE = 1–2.52.5LSB
Input voltage = 0 V at AFE = 2–3-3LSB
Input voltage = 0 V at AFE = 3–44LSB
Sample Rate15.625MHz
Analog Front End Amplifier Bandwidth100MHz
A0GainSee Figure 9-21V/V
Minimum output voltage21mV
EADC DAC
DAC range01.6V
VREF DAC reference resolution10-bit, No dithering enabled1.56mV
VREF DAC reference resolutionWith 4-bit dithering enabled97.6μV
INL–2.02.0LSB
DNLDoes not include MSB transition–1.02.1LSB
DNL at MSB transition–1.4LSB
DAC reference voltage1.581.61V
ADC12
IBIASBias current for PMBus address pins9.510.5μA
Measurement range for voltage monitoring02.5V
Internal ADC reference voltage–40 to 125 °C2.4752.5002.53V
Change in Internal ADC reference from 25°C reference voltage (5)–40 to 25 °C–0.7mV
25 to 125 °C–2.1
ADC12 INL integral nonlinearity (5)ADC_SAMPLING_SEL = 6 for all ADC12 data, 25 to 125 °C–7.5/+2.9LSB
ADC12 DNL differential nonlinearity (5)–0.7/+3.2LSB
ADC Zero Scale Error–77mV
ADC Full Scale Error–3535mV
Input bias2.5 V applied to pin200nA
Input leakage resistance (5)ADC_SAMPLING_SEL= 6 or 01MΩ
Input Capacitance (5)10pF
DIGITAL INPUTS/OUTPUTS(1)(2)
VOLLow-level output voltage(3)IOH = 4 mA, V33DIO = 3 VDGND
+ 0.25		V
VOHHigh-level output voltage (3)IOH = –4 mA, V33DIO = 3 VV33DIO – 0.6V
VIHHigh-level input voltageV33DIO = 3 V2.1V
VILLow-level input voltageV33DIO = 3 V1.1V
IOHOutput sinking current4mA
IOLOutput sourcing current–4mA
SYSTEM PERFORMANCE
TWDWatchdog time out resolutionTotal time is: TWD x (WDCTRL.PERIOD+1)13.11722.7ms
Processor master clock (MCLK)31.25MHz
tDelayDigital filter delay(4)(1 clock = 32 ns)6MCLKs
Retention period of flash content (data retention and program)TJ = 25 °C100years
f(PCLK)Internal oscillator frequency240250260MHz
Flash Read1MCLKs
ISHARECurrent share current source (See Section 9.3.15)238259μA
RSHARECurrent share resistor (See Section 9.3.15)9.7510.3kΩ
POWER ON RESET AND BROWN OUT (V33A pin, See Figure 8-3)
VGHVoltage Good High2.7V
VGLVoltage Good Low2.5V
VresVoltage at which IReset signal is valid(5)0.8V
BrownoutInternal signal warning of brownout conditions2.9V
TEMPERATURE SENSOR(5)
VTEMPVoltage range of sensor1.462.44V
Voltage resolutionVolts/°C5.9mV/°C
Temperature resolutionDegree C per bit0.1034°C/LSB
Accuracy(5)(6)–40 to 125 °C–10±510°C
Temperature range–40 to 125 °C–40125°C
ITEMPCurrent draw of sensor when active30μA
VAMBAmbient temperatureTrimmed 25 °C reading1.85V
ANALOG COMPARATOR
DACReference DAC Range02.5V
Reference Voltage2.4782.52.513V
Bits7bits
INL(5)–0.420.21LSB
DNL(5)0.060.12LSB
Offset–5.519.5mV
Reference DAC buffered output load(7)–0.51mA
Buffer offset (–0.5 mA)4.68.3mV
Buffer offset (1.0 mA)–0.0517mV
Output Range (–0.5 mA)0.22.5V
Output Range (1.0 mA)02.5V
(1) DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset.
(2) On the 40 pin package V33DIO is connected to V33D internally.
(3) The maximum total current, IOHmax and IOLmax for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. Maximum sink current per pin = –6 mA at VOL; maximum source current per pin = 6 mA at VOH.
(4) Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which has no variation associated with it, must be accounted for when calculating the system dynamic response.
(5) Characterized by design and not production tested.
(6) Ambient temperature offset value should be used from the TEMPSENCTRL register to meet accuracy.
(7) Available from reference DACs for comparators D, E, F and G.