SLUSB72D March   2013  – April 2021 UCD3138064


  1. Features
  2. Applications
  3. Description
  4. Functional Block Diagram
  5. Revision History
  6. Device Options
    1. 6.1 Device Comparison Table
    2. 6.2 Product Selection Matrix
  7. Pin Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Functions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings (1)
    2. 8.2  Handling Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Timing Characteristics
    7. 8.7  PMBus/SMBus/I2C Timing
    8. 8.8  Power On Reset (POR) / Brown Out Reset (BOR)
    9. 8.9  Typical Clock Gating Power Savings
    10. 8.10 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
      1. 9.1.1 ARM Processor
      2. 9.1.2 Memory
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  System Module
        1. Address Decoder (DEC)
        2. Memory Management Controller (MMC)
        3. System Management (SYS)
        4. Central Interrupt Module (CIM)
      2. 9.3.2  Peripherals
        1. Digital Power Peripherals
          1. Front End
          2. DPWM Module
          3. DPWM Events
          4. High Resolution DPWM
          5. Over Sampling
          6. DPWM Interrupt Generation
          7. DPWM Interrupt Scaling/Range
      3. 9.3.3  Automatic Mode Switching
        1. Phase Shifted Full Bridge Example
        2. LLC Example
        3. Mechanism For Automatic Mode Switching
      4. 9.3.4  DPWMC, Edge Generation, Intramux
      5. 9.3.5  Filter
        1. Loop Multiplexer
        2. Fault Multiplexer
      6. 9.3.6  Communication Ports
        1. SCI (UART) Serial Communication Interface
        2. PMBUS/I2C
        3. SPI
      7. 9.3.7  Real Time Clock
      8. 9.3.8  Timers
        1. 24-Bit Timer
        2. 16-Bit PWM Timers
        3. Watchdog Timer
      9. 9.3.9  General Purpose ADC12
      10. 9.3.10 Miscellaneous Analog
      11. 9.3.11 Brownout
      12. 9.3.12 Global I/O
      13. 9.3.13 Temperature Sensor Control
      14. 9.3.14 I/O Mux Control
      15. 9.3.15 Current Sharing Control
      16. 9.3.16 Temperature Reference
    4. 9.4 Device Functional Modes
      1. 9.4.1 DPWM Modes Of Operation
        1. Normal Mode
        2. Phase Shifting
        3. DPWM Multiple Output Mode
        4. DPWM Resonant Mode
      2. 9.4.2 Triangular Mode
      3. 9.4.3 Leading Edge Mode
    5. 9.5 Memory
      1. 9.5.1 Register Maps
        1. CPU Memory Map and Interrupts
          1. Memory Map (After Reset Operation)
          2. Memory Map (Normal Operation)
          3. Memory Map (System and Peripherals Blocks)
        2. Boot ROM
        3. Customer Boot Program
        4. Flash Management
        5. Synchronous Rectifier MOSFET Ramp and IDE Calculation
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration Overview
        2. DPWM Initialization for PSFB
          1. DPWM Synchronization
        3. Fixed Signals to Bridge
        4. Dynamic Signals to Bridge
        5. System Initialization for PCM
          1. Use of Front Ends and Filters in PSFB
          2. Peak Current Detection
          3. Peak Current Mode (PCM)
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Introduction To Power Supply and Layout Recommendations
    2. 11.2 3.3-V Supply Pins
    3. 11.3 Recommendation for V33 Ramp up Slew Rate for UCD3138 and UCD3138064
    4. 11.4 Recommendation for RC Time Constant of RESET Pin for UCD3138 and UCD3138064
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 EMI and EMC Mitigation Guidelines
      2. 12.1.2 BP18 Pin
      3. 12.1.3 Additional Bias Guidelines
      4. 12.1.4 UART Communication Port
    2. 12.2 Layout Example
      1. 12.2.1 UCD3138 and UCD3138064 40 Pin
      2. 12.2.2 UCD3138 and UCD3138064 64 Pin
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Fault Multiplexer

In order to allow a flexible way of mapping several fault triggering sources to all the DPWMs channels, the UCD3138x provides an extensive array of multiplexers that are united under the name Fault Mux module.

The Fault Mux Module supports the following types of mapping between all the sources of fault and all the different fault response mechanisms inside each DPWM module.

  • Many fault sources may be mapped to a single fault response mechanism. For instance an analog comparator in charge of over voltage protection, a digital comparator in charge of over current protection and an external digital fault pin can be all mapped to a Fault-A signal connected to a single FAULT MODULE and shut down DPWM1-A.
  • A single fault source can be mapped to many fault response mechanisms inside many DPWM modules. For instance an analog comparator in charge of over current protection can be mapped to DPWM-0 through DPWM-3 by way of several fault modules.
  • Many fault sources can be mapped to many fault modules inside many DPWM modules.
GUID-9CE9E874-DEC1-4392-A591-993C2B438173-low.gifFigure 9-13 Fault Mux Module

The Fault Mux Module provides a multitude of fault protection functions within the UCD3138x high-speed loop (Front End Control, Filter, DPWM and Loop Mux modules). The Fault Mux Module allows highly configurable fault generation based on digital comparators, high-speed analog comparators and external fault pins. Each of the fault inputs to the DPWM modules can be configured to one or any combination of the fault events provided in the Fault Mux Module.

Each one of the DPWM engines has four fault modules. The modules are called CBC fault module, AB fault module, A fault module and B fault module.

The internal circuitry in all the four fault modules is identical, and the difference between the modules is limited to the way the modules are attached to the DPWMs.

GUID-BC03A2EF-73DC-4AEF-85E8-FCDC37096AB8-low.gifFigure 9-14 Fault Module

All fault modules provide immediate fault detection but only once per DPWM switching cycle. Each one of the fault modules own a separate max_count and the fault flag will be set only if sequential cycle-by-cycle fault count exceeds max_count.

Once the fault flag is set, DPWMs need to be disabled by DPWM_EN going low in order to clear the fault flags. Please note, all four Fault Modules share the same DPWM_EN control, all fault flags (output of Fault Modules) will be cleared simultaneously.

All four Fault Modules share the same global FAULT_EN as well. Therefore a specific Fault Module cannot be enabled/ disabled separately.

GUID-7E3A22E4-0B4E-4AF2-BF8E-FD6892A0E974-low.gifFigure 9-15 Cycle-By-Cycle Block

Unlike Fault Modules, only one Cycle by Cycle block is available in each DPWM module.

The Cycle by Cycle block works in conjunction with CBC Fault Module and enables DPWM reaction to signals arriving from the Analog Peak current mode (PCM) module.

The Fault Mux Module supports the following basic functions:

  • 4 digital comparators using the Front End EADCs with programmable thresholds and fault generation
  • Configuration for 7 high speed analog comparators with programmable thresholds and fault generation
  • External GPIO detection control with programmable fault generation
  • Configurable DPWM fault generation for DPWM Current Limit Fault, DPWM Over-Voltage Detection Fault, DPWM A External Fault, DPWM B External Fault and DPWM IDE Flag
  • Clock Failure Detection for High and Low Frequency Oscillator blocks
  • Discontinuous Conduction Mode Detection
GUID-14F7E018-AEB1-4A61-82EA-00BF3E7B8D01-low.gifFigure 9-16 Fault Mux Block Diagram