SLUSB72D March 2013 – April 2021 UCD3138064
+3.3 V bias normally is produced by a LDO or Buck converter. +5 V (or +12 V) normally are generated by a flyback converter and it is referenced to the Power Return. A 10 µF capacitor is locally used for LDO or buck between +3.3 V and Power RTN node. From there, use a single plane (SGND) for both digital ground and analog ground. A 1Ω resistor is needed between V33D and V33A. V33D and V33DIO should be shorted externally if they are available and have a wider trace or preferably through its own power plane to connect them. As an example, a 4.7-µF decoupling capacitor is used for V33A and V33D respectively and these decoupling capacitors should be placed close to the device pins. In addition, a 10nF capacitor is used for V33A, V33D and V33DIO respectively to filter out the high frequency noise and placed as close to the pin as possible, for example the distance is less than 25mils from the capacitor to the pin V33D (or V33DIO) and from the capacitor to the pin DGND. 10 nF uses smaller package such as 0402 and low ESR capacitor. Refer to section Schematics and Layouts. There should not be any voltage delta between the DGND pins and AGND pins. Multiple vias are required to connect the extended power pad (for example, copper plane under the device power pad) to the internal single ground (SGND) plane layer. All digital and analog ground pins are directly connected to the extended power pad and connected to the internal SGND plane through vias.