SWRS170L March   2014  – May 2025 WL1807MOD , WL1837MOD

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Attributes
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  External Digital Slow Clock Requirements
    5. 7.5  Thermal Resistance Characteristics for MOC 100-Pin Package
    6. 7.6  WLAN Performance: 2.4GHz Receiver Characteristics
    7. 7.7  WLAN Performance: 2.4GHz Transmitter Power
    8. 7.8  WLAN Performance: 5GHz Receiver Characteristics
    9. 7.9  WLAN Performance: 5GHz Transmitter Power
    10. 7.10 WLAN Performance: Currents
    11. 7.11 Bluetooth Performance: BR, EDR Receiver Characteristics—In-Band Signals
    12. 7.12 Bluetooth Performance: Transmitter, BR
    13. 7.13 Bluetooth Performance: Transmitter, EDR
    14. 7.14 Bluetooth Performance: Modulation, BR
    15. 7.15 Bluetooth Performance: Modulation, EDR
    16. 7.16 Bluetooth Low Energy Performance: Receiver Characteristics – In-Band Signals
    17. 7.17 Bluetooth Low Energy Performance: Transmitter Characteristics
    18. 7.18 Bluetooth Low Energy Performance: Modulation Characteristics
    19. 7.19 Bluetooth BR and EDR Dynamic Currents
    20. 7.20 Bluetooth Low Energy Currents
    21. 7.21 Timing and Switching Characteristics
      1. 7.21.1 Power Management
        1. 7.21.1.1 Block Diagram – Internal DC-DCs
      2. 7.21.2 Power-Up and SHUTDOWN States
      3. 7.21.3 Chip Top-level Power-Up Sequence
      4. 7.21.4 WLAN Power-Up Sequence
      5. 7.21.5 Bluetooth-Bluetooth Low Energy Power-Up Sequence
      6. 7.21.6 WLAN SDIO Transport Layer
        1. 7.21.6.1 SDIO Timing Specifications
        2. 7.21.6.2 SDIO Switching Characteristics – High Rate
      7. 7.21.7 HCI UART Shared-Transport Layers for All Functional Blocks (Except WLAN)
        1. 7.21.7.1 UART 4-Wire Interface – H4
      8. 7.21.8 Bluetooth Codec-PCM (Audio) Timing Specifications
  9. 8 Detailed Description
    1. 8.1 WLAN Features
    2. 8.2 Bluetooth Features
    3. 8.3 Bluetooth Low Energy Features
    4. 8.4 Device Certification
      1. 8.4.1 FCC Certification and Statement
      2. 8.4.2 Innovation, Science, and Economic Development Canada (ISED)
      3. 8.4.3 ETSI/CE
      4. 8.4.4 MIC Certification
    5. 8.5 Module Markings
    6. 8.6 Test Grades
    7. 8.7 End Product Labeling
    8. 8.8 Manual Information to the End User
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
      1. 9.1.1 Typical Application – WL1837MOD Reference Design
      2. 9.1.2 Design Recommendations
      3. 9.1.3 RF Trace and Antenna Layout Recommendations
      4. 9.1.4 Module Layout Recommendations
      5. 9.1.5 Thermal Board Recommendations
      6. 9.1.6 Baking and SMT Recommendations
        1. 9.1.6.1 Baking Recommendations
        2. 9.1.6.2 SMT Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Tools and Software
      3. 10.1.3 Device Support Nomenclature
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 TI Module Mechanical Outline
    2. 12.2 Tape and Reel Information
      1. 12.2.1 Tape and Reel Specification
      2. 12.2.2 Packing Specification
        1. 12.2.2.1 Reel Box
        2. 12.2.2.2 Shipping Box
    3. 12.3 Packaging Information
      1. 12.3.1 PACKAGE OPTION ADDENDUM

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • MOC|100
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.21.2 Power-Up and SHUTDOWN States

The correct power-up and shutdown sequences must be followed to avoid damage to the device.

While VBAT or VIO or both are deasserted, no signals should be driven to the device. The only exception is the slow clock that is a failsafe I/O.

While VBAT, VIO, and slow clock are fed to the device, but WL_EN is deasserted (low), the device is in SHUTDOWN state. In SHUTDOWN state all functional blocks, internal DC-DCs, clocks, and LDOs are disabled.

To perform the correct power-up sequence, assert (high) WL_EN. The internal DC-DCs, LDOs, and clock start to ramp and stabilize. Stable slow clock, VIO, and VBAT are prerequisites to the assertion of one of the enable signals.

To perform the correct shut-down sequence, deassert (low) WL_EN while all the supplies to the device (VBAT, VIO, and slow clock) are still stable and available. The supplies to the chip (VBAT and VIO) can be deasserted only after both enable signals are deasserted (low).

Figure 7-2 shows the general power scheme for the module, including the power-down sequence.

WL1807MOD WL1837MOD Power-Up System
NOTE: 1. Either VBAT or VIO can come up first.
2. VBAT and VIO supplies and slow clock (SCLK), must be stable prior to EN being asserted and at all times.
When the EN is active.
3. At least 60µs is required between two successive device enables. The device is assumed to be in
shutdown state during that period, meaning all enables to the device are LOW for that minimum duration.
4. EN must be deasserted at least 10µs before VBAT or VIO supply can be lowered (order of supply turn off
after EN shutdown is immaterial).
5. EXT_32K - Failsafe I/O
Figure 7-2 Power-Up System