SBOS062C
September 2000 – January 2022
INA126
,
INA2126
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information: INA126
6.5
Thermal Information: INA2126
6.6
Electrical Characteristics
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.4
Device Functional Modes
7.4.1
Single-Supply Operation
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Setting the Gain
8.2.2.2
Offset Trimming
8.2.2.3
Input Bias Current Return
8.2.2.4
Input Common-Mode Range
8.2.2.5
Input Protection
8.2.2.6
Channel Crosstalk—Dual Version
8.2.3
Application Curves
9
Power Supply Recommendations
9.1
Low-Voltage Operation
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Development Support
11.1.1.1
PSpice® for TI
11.2
Receiving Notification of Documentation Updates
11.3
Support Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
D|8
MSOI002K
DGK|8
MPDS028E
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sbos062c_oa
sbos062c_pm
1
Features
Low quiescent current: 175 μA/channel
Wide supply range: ±1.35 V to ±18 V
Low offset voltage: 250-μV maximum
Low offset drift: 3-μV/°C maximum
Low noise: 35 nV/√
Hz
Low input bias current: 25-nA maximum
Temperature range: –40°C to +85°C
Multiple package options:
Single channel:
INA126P/PA 8-pin PDIP (P)
INA126U/UA 8-pin SOIC (D)
INA126E/EA 8-pin VSSOP (DGK)
Dual channels:
INA2126P/PA 16-pin PDIP (N)
INA2126U/UA 16-pin SOIC (D)
INA2126E/EA 16-pin SSOP (DBQ)