12ビット、RF サンプリング A/D コンバータ (ADC)" />

JAJSGI4B November   2018  – March 2021 ADC12DJ3200QML-SP

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
      2. 7.3.2 ADC Core
        1. 7.3.2.1 ADC Theory of Operation
        2. 7.3.2.2 ADC Core Calibration
        3. 7.3.2.3 ADC Overrange Detection
        4. 7.3.2.4 Code Error Rate (CER)
      3. 7.3.3 Timestamp
      4. 7.3.4 Clocking
        1. 7.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.4.3.2 Automatic SYSREF Calibration
      5. 7.3.5 Digital Down Converters (Dual-Channel Mode Only)
        1. 7.3.5.1 Numerically-Controlled Oscillator and Complex Mixer
          1. 7.3.5.1.1 NCO Fast Frequency Hopping (FFH)
          2. 7.3.5.1.2 NCO Selection
          3. 7.3.5.1.3 Basic NCO Frequency Setting Mode
          4. 7.3.5.1.4 Rational NCO Frequency Setting Mode
          5. 7.3.5.1.5 NCO Phase Offset Setting
          6. 7.3.5.1.6 NCO Phase Synchronization
        2. 7.3.5.2 Decimation Filters
        3. 7.3.5.3 Output Data Format
        4. 7.3.5.4 Decimation Settings
          1. 7.3.5.4.1 Decimation Factor
          2. 7.3.5.4.2 DDC Gain Boost
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 Transport Layer
        2. 7.3.6.2 Scrambler
        3. 7.3.6.3 Link Layer
          1. 7.3.6.3.1 Code Group Synchronization (CGS)
          2. 7.3.6.3.2 Initial Lane Alignment Sequence (ILAS)
          3. 7.3.6.3.3 8b, 10b Encoding
          4. 7.3.6.3.4 Frame and Multiframe Monitoring
        4. 7.3.6.4 Physical Layer
          1. 7.3.6.4.1 SerDes Pre-Emphasis
        5. 7.3.6.5 JESD204B Enable
        6. 7.3.6.6 Multi-Device Synchronization and Deterministic Latency
        7. 7.3.6.7 Operation in Subclass 0 Systems
      7. 7.3.7 Alarm Monitoring
        1. 7.3.7.1 NCO Upset Detection
        2. 7.3.7.2 Clock Upset Detection
      8. 7.3.8 Temperature Monitoring Diode
      9. 7.3.9 Analog Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 JESD204B Modes
        1. 7.4.3.1 JESD204B Output Data Formats
        2. 7.4.3.2 Dual DDC and Redundant Data Mode
      4. 7.4.4 Power-Down Modes
      5. 7.4.5 Test Modes
        1. 7.4.5.1 Serializer Test-Mode Details
        2. 7.4.5.2 PRBS Test Modes
        3. 7.4.5.3 Ramp Test Mode
        4. 7.4.5.4 Short and Long Transport Test Mode
          1. 7.4.5.4.1 Short Transport Test Pattern
          2. 7.4.5.4.2 Long Transport Test Pattern
        5. 7.4.5.5 D21.5 Test Mode
        6. 7.4.5.6 K28.5 Test Mode
        7. 7.4.5.7 Repeated ILA Test Mode
        8. 7.4.5.8 Modified RPAT Test Mode
      6. 7.4.6 Calibration Modes and Trimming
        1. 7.4.6.1 Foreground Calibration Mode
        2. 7.4.6.2 Background Calibration Mode
        3. 7.4.6.3 Low-Power Background Calibration (LPBG) Mode
      7. 7.4.7 Offset Calibration
      8. 7.4.8 Trimming
      9. 7.4.9 Offset Filtering
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
      2. 7.6.2 SYSREF Calibration Registers (0x2B0 to 0x2BF)
      3. 7.6.3 Alarm Registers (0x2C0 to 0x2C2)
  8. Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Analog Inputs
      2. 8.1.2 Analog Input Bandwidth
      3. 8.1.3 Clocking
      4. 8.1.4 Radiation Environment Recommendations
        1. 8.1.4.1 Single Event Latch-Up (SEL)
        2. 8.1.4.2 Single Event Functional Interrupt (SEFI)
        3. 8.1.4.3 Single Event Upset (SEU)
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 RF Input Signal Path
        2. 8.2.2.2 Calculating Values of AC-Coupling Capacitors
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
      1.      Power Supply Recommendations
        1. 9.1 Power Sequencing
  9. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
      1.      Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • ZMX|196
  • NWE|196
サーマルパッド・メカニカル・データ
発注情報

Register Descriptions

7.6.1.1 Standard SPI-3.0 (0x000 to 0x00F)

Table 7-45 Standard SPI-3.0 Registers
ADDRESSRESETACRONYMREGISTER NAMESECTION
0x0000x30CONFIG_AConfiguration A RegisterSection 7.6.1.2
0x001UndefinedRESERVEDRESERVED
0x0020x00DEVICE_CONFIGDevice Configuration RegisterSection 7.6.1.3
0x0030x03CHIP_TYPEChip Type RegisterSection 7.6.1.4
0x004-0x0050x0020CHIP_IDChip ID RegistersSection 7.6.1.5
0x0060x0ACHIP_VERSIONChip Version RegisterSection 7.6.1.6
0x007-0x00BUndefinedRESERVEDRESERVED
0x00C-0x00D0x0451VENDOR_IDVendor Identification RegisterSection 7.6.1.7
0x00E-0x00FUndefinedRESERVEDRESERVED

7.6.1.2 Configuration A Register (address = 0x000) [reset = 0x30]

Figure 7-26 Configuration A Register (CONFIG_A)
76543210
SOFT_RESETRESERVEDADDR_ASCSDO_ACTIVERESERVED
R/W-0R-0R/W-1R-1R-0000
Table 7-46 CONFIG_A Field Descriptions
BitFieldTypeResetDescription
7SOFT_RESETR/W0Setting this bit results in a full reset of the device. This bit is self-clearing. After writing this bit, the device may take up to 750 ns to reset. During this time, do not perform any SPI transactions.
6RESERVEDR0RESERVED
5ADDR_ASCR/W10: Descend – decrement address while streaming reads/writes
1: Ascend – increment address while streaming reads/writes (default)
4SDO_ACTIVER1Always returns 1, indicating that the device always uses 4-wire SPI mode.
3-0RESERVEDR0000RESERVED

7.6.1.3 Device Configuration Register (address = 0x002) [reset = 0x00]

Figure 7-27 Device Configuration Register (DEVICE_CONFIG)
76543210
RESERVEDMODE
R-0000 00R/W-00
Table 7-47 DEVICE_CONFIG Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR0000 00RESERVED
1-0MODER/W00The SPI 3.0 specification lists 1 as the low-power functional mode, 2 as the low-power fast resume, and 3 as power-down. This device does not support these modes.
0: Normal operation – full power and full performance (default)
1: Normal operation – full power and full performance
2: Power down - everything is powered down. Only use this setting for brief periods of time to calibrate the on-chip temperature diode measurement. See the Recommended Operating Conditions table for more information.
3: Power down - everything is powered down. Only use this setting for brief periods of time to calibrate the on-chip temperature diode measurement. See the Recommended Operating Conditions table for more information.

7.6.1.4 Chip Type Register (address = 0x003) [reset = 0x03]

Figure 7-28 Chip Type Register (CHIP_TYPE)
76543210
RESERVEDCHIP_TYPE
R-0000R-0011
Table 7-48 CHIP_TYPE Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0000RESERVED
3-0CHIP_TYPER0011Always returns 0x3, indicating that the device is a high-speed ADC.

7.6.1.5 Chip ID Register (address = 0x004 to 0x005) [reset = 0x0020]

Figure 7-29 Chip ID Register (CHIP_ID)
15141312111098
CHIP_ID[15:8]
R-0x00h
76543210
CHIP_ID[7:0]
R-0x20h
Table 7-49 CHIP_ID Field Descriptions
BitFieldTypeResetDescription
15-0CHIP_IDR0x0020hAlways returns 0x0020, indicating that this device is an ADC12DJ3200QML-SP device.

7.6.1.6 Chip Version Register (address = 0x006) [reset = 0x01]

Figure 7-30 Chip Version Register (CHIP_VERSION)
76543210
CHIP_VERSION
R-0000 1010
Table 7-50 CHIP_VERSION Field Descriptions
BitFieldTypeResetDescription
7-0CHIP_VERSIONR0000 1010Chip version, returns 0x0A.

7.6.1.7 Vendor Identification Register (address = 0x00C to 0x00D) [reset = 0x0451]

Figure 7-31 Vendor Identification Register (VENDOR_ID)
15141312111098
VENDOR_ID[15:8]
R-0x04h
76543210
VENDOR_ID[7:0]
R-0x51h
Table 7-51 VENDOR_ID Field Descriptions
BitFieldTypeResetDescription
15-0VENDOR_IDR0x0451hAlways returns 0x0451 (TI vendor ID).

7.6.1.8 User SPI Configuration (0x010 to 0x01F)

Table 7-52 User SPI Configuration Registers
ADDRESSRESETACRONYMREGISTER NAMESECTION
0x0100x00USR0User SPI Configuration RegisterSection 7.6.1.9
0x011-0x01FUndefinedRESERVEDRESERVED

7.6.1.9 User SPI Configuration Register (address = 0x010) [reset = 0x00]

Figure 7-32 User SPI Configuration Register (USR0)
76543210
RESERVEDADDR_HOLD
R-0000 000R/W-0
Table 7-53 USR0 Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0000 000RESERVED
0ADDR_HOLDR/W00: Use the ADDR_ASC bit to define what happens to the address during streaming (default)
1: Address remains static throughout streaming operation; this setting is useful for reading/writing calibration vector information at the CAL_DATA register

7.6.1.10 Miscellaneous Analog Registers (0x020 to 0x047)

Table 7-54 Miscellaneous Analog Registers
ADDRESSRESETACRONYMREGISTER NAMESECTION
0x020-0x028UndefinedRESERVEDRESERVED
0x0290x00CLK_CTRL0Clock Control Register 0Section 7.6.1.11
0x02A0x20CLK_CTRL1Clock Control Register 1Section 7.6.1.12
0x02BUndefinedRESERVEDRESERVED
0x02C-0x02EUndefinedSYSREF_POSSYSREF Capture Position RegisterSection 7.6.1.13
0x02FUndefinedRESERVEDRESERVED
0x030-0x0310xA000FS_RANGE_AINA Full-Scale Range Adjust RegisterSection 7.6.1.14
0x032-0x0330xA000FS_RANGE_BINB Full-Scale Range Adjust RegisterSection 7.6.1.15
0x034-0x037UndefinedRESERVEDRESERVED
0x0380x00BG_BYPASSInternal Reference Bypass RegisterSection 7.6.1.16
0x039-0x03AUndefinedRESERVEDRESERVED
0x03B0x00SYNC_CTRLTMSTP± Control RegisterSection 7.6.1.17
0x03C-0x047UndefinedRESERVEDRESERVED

7.6.1.11 Clock Control Register 0 (address = 0x029) [reset = 0x00]

Figure 7-33 Clock Control Register 0 (CLK_CTRL0)
76543210
RESERVEDSYSREF_PROC_ENSYSREF_RECV_ENSYSREF_ZOOMSYSREF_SEL
R/W-0R/W-0R/W-0R/W-0R/W-0000
Table 7-55 CLK_CTRL0 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0RESERVED
6SYSREF_PROC_ENR/W0This bit enables the SYSREF processor. This bit must be set to allow the device to process SYSREF events. SYSREF_RECV_EN must be set before setting SYSREF_PROC_EN.
5SYSREF_RECV_ENR/W0Set this bit to enable the SYSREF receiver circuit.
4SYSREF_ZOOMR/W0Set this bit to zoom in the SYSREF strobe status (affects SYSREF_POS).
3-0SYSREF_SELR/W0000Set this field to select which SYSREF delay to use. Set this field based on the results returned by SYSREF_POS. Set this field to 0 to use SYSREF calibration.

7.6.1.12 Clock Control Register 1 (address = 0x02A) [reset = 0x00]

Figure 7-34 Clock Control Register 1 (CLK_CTRL1)
76543210
RESERVEDDEVCLK_LVPECL_ENSYSREF_LVPECL_ENSYSREF_INVERTED
R/W-0010 0R/W-0R/W-0R/W-0
Table 7-56 CLK_CTRL1 Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR/W0010 0RESERVED
2DEVCLK_LVPECL_ENR/W0Activate low-voltage PECL mode for DEVCLK.
1SYSREF_LVPECL_ENR/W0Activate low-voltage PECL mode for SYSREF.
0SYSREF_INVERTEDR/W0Inverts the SYSREF signal used for alignment.

7.6.1.13 SYSREF Capture Position Register (address = 0x02C-0x02E) [reset = Undefined]

Figure 7-35 SYSREF Capture Position Register (SYSREF_POS)
2322212019181716
SYSREF_POS[23:16]
R-Undefined
15141312111098
SYSREF_POS[15:8]
R-Undefined
76543210
SYSREF_POS[7:0]
R-Undefined
Table 7-57 SYSREF_POS Field Descriptions
BitFieldTypeResetDescription
23-0SYSREF_POSRUndefinedThis field returns a 24-bit status value that indicates the position of the SYSREF edge with respect to DEVCLK. Use this field to program SYSREF_SEL.

7.6.1.14 INA Full-Scale Range Adjust Register (address = 0x030-0x031) [reset = 0xA000]

Figure 7-36 INA Full-Scale Range Adjust Register (FS_RANGE_A)
15141312111098
FS_RANGE_A[15:8]
R/W-0xA0h
76543210
FS_RANGE_A[7:0]
R/W-0x00h
Table 7-58 FS_RANGE_A Field Descriptions
BitFieldTypeResetDescription
15-0FS_RANGE_AR/W0xA000hThis field enables adjustment of the analog full-scale range for INA.
0x0000: Settings below 0x2000 may result in degraded device performance
0x2000: 500 mVPP - Recommended minimum setting
0xA000: 800 mVPP (default)
0xFFFF: 1000 mVPP

7.6.1.15 INB Full-Scale Range Adjust Register (address = 0x032-0x033) [reset = 0xA000]

Figure 7-37 INB Full Scale Range Adjust Register (FS_RANGE_B)
15141312111098
FS_RANGE_B[15:8]
R/W-0xA0
76543210
FS_RANGE_B[7:0]
R/W-0x00
Table 7-59 FS_RANGE_B Field Descriptions
BitFieldTypeResetDescription
15-0FS_RANGE_BR/W0xA000hThis field enables adjustment of the analog full-scale range for INB.
0x0000: Settings below 0x2000 may result in degraded device performance
0x2000: 500 mVPP - Recommended minimum setting
0xA000: 800 mVPP (default)
0xFFFF: 1000 mVPP

7.6.1.16 Internal Reference Bypass Register (address = 0x038) [reset = 0x00]

Figure 7-38 Internal Reference Bypass Register (BG_BYPASS)
76543210
RESERVEDBG_BYPASS
R/W-0000 000R/W-0
Table 7-60 BG_BYPASS Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0000 000RESERVED
0BG_BYPASSR/W0When set, VA11 is used as the voltage reference instead of the internal reference.

7.6.1.17 TMSTP± Control Register (address = 0x03B) [reset = 0x00]

Figure 7-39 TMSTP± Control Register (TMSTP_CTRL)
76543210
RESERVEDTMSTP_LVPECL_ENTMSTP_RECV_EN
R/W-0000 00R/W-0R/W-0
Table 7-61 TMSTP_CTRL Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W0000 00RESERVED
1TMSTP_LVPECL_ENR/W0When set, this bit activates the low-voltage PECL mode for the differential TMSTP± input.
0TMSTP_RECV_ENR/W0This bit enables the differential TMSTP± input.

7.6.1.18 Serializer Registers (0x048 to 0x05F)

Table 7-62 Serializer Registers
ADDRESSRESETACRONYMREGISTER NAMESECTION
0x0480x00SER_PESerializer Pre-Emphasis Control RegisterSection 7.6.1.19
0x049-0x05FUndefinedRESERVEDRESERVED

7.6.1.19 Serializer Pre-Emphasis Control Register (address = 0x048) [reset = 0x00]

Figure 7-40 Serializer Pre-Emphasis Control Register (SER_PE)
76543210
RESERVEDSER_PE
R/W-0000R/W-0000
Table 7-63 SER_PE Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0000RESERVED
3-0SER_PER/W0000This field sets the pre-emphasis for the serial lanes to compensate for the low-pass response of the PCB trace. This setting is a global setting that affects all 16 lanes.

7.6.1.20 Calibration Registers (0x060 to 0x0FF)

Table 7-64 Calibration Registers
ADDRESSRESETACRONYMREGISTER NAMESECTION
0x0600x01INPUT_MUXInput Mux Control RegisterSection 7.6.1.21
0x0610x01CAL_ENCalibration Enable RegisterSection 7.6.1.22
0x0620x01CAL_CFG0Calibration Configuration 0 RegisterSection 7.6.1.23
0x063-0x069UndefinedRESERVEDRESERVED
0x06AUndefinedCAL_STATUSCalibration Status RegisterSection 7.6.1.24
0x06B0x00CAL_PIN_CFGCalibration Pin Configuration RegisterSection 7.6.1.25
0x06C0x01CAL_SOFT_TRIGCalibration Software Trigger RegisterSection 7.6.1.26
0x06DUndefinedRESERVEDRESERVED
0x06E0x88CAL_LPLow-Power Background Calibration RegisterSection 7.6.1.27
0x06FUndefinedRESERVEDRESERVED
0x0700x00CAL_DATA_ENCalibration Data Enable RegisterSection 7.6.1.28
0x071UndefinedCAL_DATACalibration Data RegisterSection 7.6.1.29
0x072-0x079UndefinedRESERVEDRESERVED
0x07AUndefinedGAIN_TRIM_AChannel A Gain Trim RegisterSection 7.6.1.30
0x07BUndefinedGAIN_TRIM_BChannel B Gain Trim RegisterSection 7.6.1.31
0x07CUndefinedBG_TRIMBand-Gap Reference Trim RegisterSection 7.6.1.32
0x07DUndefinedRESERVEDRESERVED
0x07EUndefinedRTRIM_AVINA Input Resistor Trim RegisterSection 7.6.1.33
0x07FUndefinedRTRIM_BVINB Input Resistor Trim RegisterSection 7.6.1.34
0x080UndefinedTADJ_A_FG90Timing Adjustment for A-ADC, Single-Channel Mode, Foreground Calibration RegisterSection 7.6.1.35
0x081UndefinedTADJ_B_FG0Timing Adjustment for B-ADC, Single-Channel Mode, Foreground Calibration RegisterSection 7.6.1.36
0x082UndefinedTADJ_A_BG90Timing Adjustment for A-ADC, Single-Channel Mode, Background Calibration RegisterSection 7.6.1.37
0x083UndefinedTADJ_C_BG0Timing Adjustment for C-ADC, Single-Channel Mode, Background Calibration RegisterSection 7.6.1.39
0x084UndefinedTADJ_C_BG90Timing Adjustment for C-ADC, Single-Channel Mode, Background Calibration RegisterSection 7.6.1.39
0x085UndefinedTADJ_B_BG0Timing Adjustment for B-ADC, Single-Channel Mode, Background Calibration RegisterSection 7.6.1.40
0x086UndefinedTADJ_ATiming Adjustment for A-ADC, Dual-Channel Mode RegisterSection 7.6.1.41
0x087UndefinedTADJ_CATiming Adjustment for C-ADC Acting for A-ADC, Dual-Channel Mode RegisterSection 7.6.1.42
0x088UndefinedTADJ_CBTiming Adjustment for C-ADC Acting for B-ADC, Dual-Channel Mode RegisterSection 7.6.1.43
0x089UndefinedTADJ_BTiming Adjustment for B-ADC, Dual-Channel Mode RegisterSection 7.6.1.44
0x08A-0x08BUndefinedOADJ_A_INAOffset Adjustment for A-ADC and INA RegisterSection 7.6.1.45
0x08C-0x08DUndefinedOADJ_A_INBOffset Adjustment for A-ADC and INB RegisterSection 7.6.1.46
0x08E-0x08FUndefinedOADJ_C_INAOffset Adjustment for C-ADC and INA RegisterSection 7.6.1.47
0x090-0x091UndefinedOADJ_C_INBOffset Adjustment for C-ADC and INB RegisterSection 7.6.1.48
0x092-0x093UndefinedOADJ_B_INAOffset Adjustment for B-ADC and INA RegisterSection 7.6.1.49
0x094-0x095UndefinedOADJ_B_INBOffset Adjustment for B-ADC and INB RegisterSection 7.6.1.50
0x096UndefinedRESERVEDRESERVED
0x0970x000SFILT0Offset Filtering Control 0Section 7.6.1.51
0x0980x33OSFILT1Offset Filtering Control 1Section 7.6.1.52
0x099-0x0FFUndefinedRESERVEDRESERVED

7.6.1.21 Input Mux Control Register (address = 0x060) [reset = 0x01]

Figure 7-41 Input Mux Control Register (INPUT_MUX)
76543210
RESERVEDDUAL_INPUTRESERVEDSINGLE_INPUT
R/W-000R/W-0R/W-00R/W-01
Table 7-65 INPUT_MUX Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W000RESERVED
4DUAL_INPUTR/W0This bit selects inputs for dual-channel modes. If JMODE is selecting a single-channel mode, this register has no effect.
0: A channel samples INA, B channel samples INB (no swap, default)
1: A channel samples INB, B channel samples INA (swap)
3-2RESERVEDR/W00RESERVED
1-0SINGLE_INPUTR/W01Thid field defines which input is sampled in single-channel mode. If JMODE is not selecting a single-channel mode, this register has no effect.
0: Reserved
1: INA is used (default)
2: INB is used
3: Reserved

7.6.1.22 Calibration Enable Register (address = 0x061) [reset = 0x01]

Figure 7-42 Calibration Enable Register (CAL_EN)
76543210
RESERVEDCAL_EN
R/W-0000 000R/W-1
Table 7-66 CAL_EN Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0000 000RESERVED
0CAL_ENR/W1Calibration enable. Set this bit high to run calibration. Set this bit low to hold the calibration in reset to program new calibration settings. Clearing CAL_EN also resets the clock dividers that clock the digital block and JESD204B interface.

Some calibration registers require clearing CAL_EN before making any changes. All registers with this requirement contain a note in their descriptions. After changing the registers, set CAL_EN to re-run calibration with the new settings.

Always set CAL_EN before setting JESD_EN. Always clear JESD_EN before clearing CAL_EN.

7.6.1.23 Calibration Configuration 0 Register (address = 0x062) [reset = 0x01]

Only change this register when CAL_EN is 0.

Figure 7-43 Calibration Configuration 0 Register (CAL_CFG0)
76543210
RESERVEDCAL_OSFILTCAL_BGOSCAL_OSCAL_BGCAL_FG
R/W-000R/W-0R/W-0R/W-0R/W-0R/W-1
Table 7-67 CAL_CFG0 Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W0000RESERVED
4CAL_OSFILTR/W0Enable offset filtering by setting this bit high.
3CAL_BGOSR/W00 : Disables background offset calibration (default)
1: Enables background offset calibration (requires CAL_BG to be set).
2CAL_OSR/W00 : Disables foreground offset calibration (default)
1: Enables foreground offset calibration (requires CAL_FG to be set)
1CAL_BGR/W00 : Disables background calibration (default)
1: Enables background calibration
0CAL_FGR/W10 : Resets calibration values, skips foreground calibration
1: Resets calibration values, then runs foreground calibration (default)

7.6.1.24 Calibration Status Register (address = 0x06A) [reset = Undefined]

Figure 7-44 Calibration Status Register (CAL_STATUS)
76543210
RESERVEDCAL_STOPPEDFG_DONE
RRR
Table 7-68 CAL_STATUS Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDRRESERVED
1CAL_STOPPEDRThis bit returns a 1 when the background calibration has successfully stopped at the requested phase. This bit returns a 0 when calibration starts operating again. If background calibration is disabled, this bit is set when foreground calibration is completed or skipped.
0FG_DONERThis bit is set high when the foreground calibration completes.

7.6.1.25 Calibration Pin Configuration Register (address = 0x06B) [reset = 0x00]

Figure 7-45 Calibration Pin Configuration Register (CAL_PIN_CFG)
76543210
RESERVEDCAL_STATUS_SELCAL_TRIG_EN
R/W-0000 0R/W-00R/W-0
Table 7-69 CAL_PIN_CFG Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR/W0000 0RESERVED
2-1CAL_STATUS_SELR/W000: CALSTAT output pin matches FG_DONE
1: RESERVED
2: CALSTAT output pin matches ALARM
3: CALSTAT output pin is always low
0CAL_TRIG_ENR/W0Choose the hardware or software trigger source with this bit.

0: Use the CAL_SOFT_TRIG register for the calibration trigger; the CAL_TRIG input is disabled (ignored)
1: Use the CAL_TRIG input for the calibration trigger; the CAL_SOFT_TRIG register is ignored

7.6.1.26 Calibration Software Trigger Register (address = 0x06C) [reset = 0x01]

Figure 7-46 Calibration Software Trigger Register (CAL_SOFT_TRIG)
76543210
RESERVEDCAL_SOFT_TRIG
R/W-0000 000R/W-1
Table 7-70 CAL_SOFT_TRIG Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0000 000RESERVED
0CAL_SOFT_TRIGR/W1CAL_SOFT_TRIG is a software bit to provide functionality of the CAL_TRIG input. Program CAL_TRIG_EN = 0 to use CAL_SOFT_TRIG for the calibration trigger. If no calibration trigger is needed, leave CAL_TRIG_EN = 0 and CAL_SOFT_TRIG = 1 (trigger is set high).

7.6.1.27 Low-Power Background Calibration Register (address = 0x06E) [reset = 0x88]

Figure 7-47 Low-Power Background Calibration Register (CAL_LP)
76543210
LP_SLEEP_DLYLP_WAKE_DLYRESERVEDLP_TRIGLP_EN
R/W-010R/W-01R/W-0R/W-0R/W-0
Table 7-71 CAL_LP Field Descriptions
BitFieldTypeResetDescription
7-5LP_SLEEP_DLYR/W010Adjust how long an ADC sleeps before waking up for calibration (only applies when LP_EN = 1 and LP_TRIG = 0). Values below 4 are not recommended because of limited overall power reduction benefits.
0: Sleep delay = (23 + 1) × 256 × tDEVCLK
1: Sleep delay = (215 + 1) × 256 × tDEVCLK
2: Sleep delay = (218 + 1) × 256 × tDEVCLK
3: Sleep delay = (221 + 1) × 256 × tDEVCLK
4: Sleep delay = (224 + 1) × 256 × tDEVCLK : default is approximately 1338 ms with a 3.2-GHz clock
5: Sleep delay = (227 + 1) × 256 × tDEVCLK
6: Sleep delay = (230 + 1) × 256 × tDEVCLK
7: Sleep delay = (233 + 1) × 256 × tDEVCLK
4-3LP_WAKE_DLYR/W01Adjust how much time is given up for settling before calibrating an ADC after wake-up (only applies when LP_EN = 1). Values lower than 1 are not recommended because there is insufficient time for the core to stabilize before calibration begins.
0:Wake Delay = (23 + 1) × 256 × tDEVCLK
1: Wake Delay = (218 + 1) × 256 × tDEVCLK : default is approximately 21 ms with a 3.2-GHz clock
2: Wake Delay = (221 + 1) × 256 × tDEVCLK
3: Wake Delay = (224 + 1) × 256 × tDEVCLK
2RESERVEDR/W0RESERVED
1LP_TRIGR/W00: ADC sleep duration is set by LP_SLEEP_DLY (autonomous mode)
1: ADCs sleep until woken by a trigger; an ADC is awoken when the calibration trigger (CAL_SOFT_TRIG bit or CAL_TRIG input) is low
0LP_ENR/W00: Disables low-power background calibration (default)
1: Enables low-power background calibration (only applies when CAL_BG = 1)

7.6.1.28 Calibration Data Enable Register (address = 0x070) [reset = 0x00]

Figure 7-48 Calibration Data Enable Register (CAL_DATA_EN)
76543210
RESERVEDCAL_DATA_EN
R/W-0000 000R/W-0
Table 7-72 CAL_DATA_EN Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0000 000RESERVED
0CAL_DATA_ENR/W0Set this bit to enable the CAL_DATA register to enable reading and writing of calibration data; see the calibration data register for more information.

7.6.1.29 Calibration Data Register (address = 0x071) [reset = Undefined]

Figure 7-49 Calibration Data Register (CAL_DATA)
76543210
CAL_DATA
R/W
Table 7-73 CAL_DATA Field Descriptions
BitFieldTypeResetDescription
7-0CAL_DATAR/WUndefinedAfter setting CAL_DATA_EN, repeated reads of this register return all calibration values for the ADCs. Repeated writes of this register input all calibration values for the ADCs. To read the calibration data, read the register 673 times. To write the vector, write the register 673 times with previously stored calibration data.
To speed up the read/write operation, set ADDR_HOLD = 1 and use the streaming read or write process.
Accessing the CAL_DATA register when CAL_STOPPED = 0 corrupts the calibration. Also, stopping the process before reading or writing 673 times leaved the calibration data in an invalid state.

7.6.1.30 Channel A Gain Trim Register (address = 0x07A) [reset = Undefined]

Figure 7-50 Channel A Gain Trim Register (GAIN_TRIM_A)
76543210
GAIN_TRIM_A
R/W
Table 7-74 GAIN_TRIM_A Field Descriptions
BitFieldTypeResetDescription
7-0GAIN_TRIM_AR/WUndefinedThis register enables gain trim of channel A. After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.31 Channel B Gain Trim Register (address = 0x07B) [reset = Undefined]

Figure 7-51 Channel B Gain Trim Register (GAIN_TRIM_B)
76543210
GAIN_TRIM_B
R/W
Table 7-75 GAIN_TRIM_B Field Descriptions
BitFieldTypeResetDescription
7-0GAIN_TRIM_BR/WUndefinedThis register enables gain trim of channel B. After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.32 Band-Gap Reference Trim Register (address = 0x07C) [reset = Undefined]

Figure 7-52 Band-Gap Reference Trim Register (BG_TRIM)
76543210
RESERVEDBG_TRIM
R/W-0000R/W
Table 7-76 BG_TRIM Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0000RESERVED
3-0BG_TRIMR/WUndefinedThis register enables the internal band-gap reference to be trimmed. After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.33 VINA Input Resistor Trim Register (address = 0x07E) [reset = Undefined]

Figure 7-53 VINA Input Resistor Trim Register (RTRIM_A)
76543210
RTRIM
R/W
Table 7-77 RTRIM_A Field Descriptions
BitFieldTypeResetDescription
7-0RTRIM_AR/WUndefinedThis register controls the VINA ADC input termination trim. After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.34 VINB Input Resistor Trim Register (address = 0x07F) [reset = Undefined]

Figure 7-54 VINB Input Resistor Trim Register (RTRIM_B)
76543210
RTRIM
R/W
Table 7-78 RTRIM_B Field Descriptions
BitFieldTypeResetDescription
7-0RTRIM_BR/WUndefinedThis register controls the VINB ADC input termination trim. After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.35 Timing Adjust for A-ADC, Single-Channel Mode, Foreground Calibration Register (address = 0x080) [reset = Undefined]

Figure 7-55 Register (TADJ_A_FG90)
76543210
TADJ_A_FG90
R/W
Table 7-79 TADJ_A_FG90 Field Descriptions
BitFieldTypeResetDescription
7-0TADJ_A_FG90R/WUndefinedThis register (and other subsequent TADJ* registers) are used to adjust the sampling instant of each ADC core. Different TADJ registers apply to different ADCs under different modes or phases of background calibration. After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.36 Timing Adjust for B-ADC, Single-Channel Mode, Foreground Calibration Register (address = 0x081) [reset = Undefined]

Figure 7-56 Register (TADJ_B_FG0)
76543210
TADJ_B_FG0
R/W
Table 7-80 TADJ_B_FG0 Field Descriptions
BitFieldTypeResetDescription
7-0TADJ_B_FG0R/WUndefinedThis register (and other subsequent TADJ* registers) are used to adjust the sampling instant of each ADC core. Different TADJ registers apply to different ADCs under different modes or phases of background calibration. After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.37 Timing Adjust for A-ADC, Single-Channel Mode, Background Calibration Register (address = 0x082) [reset = Undefined]

Figure 7-57 Register (TADJ_A_BG90)
76543210
TADJ_A_BG90
R/W
Table 7-81 TADJ_B_FG0 Field Descriptions
BitFieldTypeResetDescription
7-0TADJ_A_BG90R/WUndefinedThis register (and other subsequent TADJ* registers) are used to adjust the sampling instant of each ADC core. Different TADJ registers apply to different ADCs under different modes or phases of background calibration. After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.38 Timing Adjust for C-ADC, Single-Channel Mode, Background Calibration Register (address = 0x083) [reset = Undefined]

Figure 7-58 Timing Adjust for C-ADC, Single-Channel Mode, Background Calibration Register (TADJ_C_BG0)
76543210
TADJ_C_BG0
R/W
Table 7-82 TADJ_B_FG0 Field Descriptions
BitFieldTypeResetDescription
7-0TADJ_C_BG0R/WUndefinedThis register (and other subsequent TADJ* registers) are used to adjust the sampling instant of each ADC core. Different TADJ registers apply to different ADCs under different modes or phases of background calibration. After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.39 Timing Adjust for C-ADC, Single-Channel Mode, Background Calibration Register (address = 0x084) [reset = Undefined]

Figure 7-59 Timing Adjust for C-ADC, Single-Channel Mode, Background Calibration Register (TADJ_C_BG90)
76543210
TADJ_C_BG90
R/W
Table 7-83 TADJ_B_FG0 Field Descriptions
BitFieldTypeResetDescription
7-0TADJ_C_BG90R/WUndefinedThis register (and other subsequent TADJ* registers) are used to adjust the sampling instant of each ADC core. Different TADJ registers apply to different ADCs under different modes or phases of background calibration. After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.40 Timing Adjust for B-ADC, Single-Channel Mode, Background Calibration Register (address = 0x085) [reset = Undefined]

Figure 7-60 Timing Adjust for B-ADC, Single-Channel Mode, Background Calibration Register (TADJ_B_BG0)
76543210
TADJ_B_BG0
R/W
Table 7-84 TADJ_B_FG0 Field Descriptions
BitFieldTypeResetDescription
7-0TADJ_B_BG0R/WUndefinedThis register (and other subsequent TADJ* registers) are used to adjust the sampling instant of each ADC core. Different TADJ registers apply to different ADCs under different modes or phases of background calibration. After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.41 Timing Adjust for A-ADC, Dual-Channel Mode Register (address = 0x086) [reset = Undefined]

Figure 7-61 Timing Adjust for A-ADC, Dual-Channel Mode Register (TADJ_A)
76543210
TADJ_A
R/W
Table 7-85 TADJ_A Field Descriptions
BitFieldTypeResetDescription
7-0TADJ_AR/WUndefinedThis register (and other subsequent TADJ* registers) are used to adjust the sampling instant of each ADC core. Different TADJ registers apply to different ADCs under different modes or phases of background calibration. After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.42 Timing Adjust for C-ADC Acting for A-ADC, Dual-Channel Mode Register (address = 0x087) [reset = Undefined]

Figure 7-62 Timing Adjust for C-ADC Acting for A-ADC, Dual-Channel Mode Register (TADJ_CA)
76543210
TADJ_CA
R/W
Table 7-86 TADJ_CA Field Descriptions
BitFieldTypeResetDescription
7-0TADJ_CAR/WUndefinedThis register (and other subsequent TADJ* registers) are used to adjust the sampling instant of each ADC core. Different TADJ registers apply to different ADCs under different modes or phases of background calibration. After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.43 Timing Adjust for C-ADC Acting for B-ADC, Dual-Channel Mode Register (address = 0x088) [reset = Undefined]

Figure 7-63 Timing Adjust for C-ADC Acting for B-ADC, Dual-Channel Mode Register (TADJ_CB)
76543210
TADJ_CB
R/W
Table 7-87 TADJ_CB Field Descriptions
BitFieldTypeResetDescription
7-0TADJ_CBR/WUndefinedThis register (and other subsequent TADJ* registers) are used to adjust the sampling instant of each ADC core. Different TADJ registers apply to different ADCs under different modes or phases of background calibration. After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.44 Timing Adjust for B-ADC, Dual-Channel Mode Register (address = 0x089) [reset = Undefined]

Figure 7-64 Timing Adjust for B-ADC, Dual-Channel Mode Register (TADJ_B)
76543210
TADJ_B
R/W
Table 7-88 TADJ_B Field Descriptions
BitFieldTypeResetDescription
7-0TADJ_BR/WUndefinedThis register (and other subsequent TADJ* registers) are used to adjust the sampling instant of each ADC core. Different TADJ registers apply to different ADCs under different modes or phases of background calibration. After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.45 Offset Adjustment for A-ADC and INA Register (address = 0x08A-0x08B) [reset = Undefined]

Figure 7-65 Offset Adjustment for A-ADC and INA Register (OADJ_A_INA)
15141312111098
RESERVEDOADJ_A_INA[11:8]
R/W-0000R/W
76543210
OADJ_A_INA[7:0]
R/W
Table 7-89 OADJ_A_INA Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/W0000RESERVED
11-0OADJ_A_INAR/WUndefinedOffset adjustment value for ADC0 (A-ADC) applied when ADC0 samples INA. The format is unsigned. After reset, the factory-trimmed value can be read and adjusted as required.

Important notes:
  • Never write OADJ* registers while foreground calibration is underway
  • Never write OADJ* registers if CAL_BG and CAL_BGOS are set
  • If CAL_OS = 1 and CAL_BGOS = 0, only read OADJ* registers if FG_DONE = 1
  • If CAL_BG = 1 and CAL_BGOS = 1, only read OADJ* register if CAL_STOPPED = 1

7.6.1.46 Offset Adjustment for A-ADC and INB Register (address = 0x08C-0x08D) [reset = Undefined]

Figure 7-66 Offset Adjustment for A-ADC and INB Register (OADJ_A_INB)
15141312111098
RESERVEDOADJ_A_INB[11:8]
R/W-0000R/W
76543210
OADJ_A_INB[7:0]
R/W
Table 7-90 OADJ_A_INB Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/W0000RESERVED
11-0OADJ_A_INBR/WUndefinedOffset adjustment value for ADC0 (A-ADC) applied when ADC0 samples INB. The format is unsigned. After reset, the factory-trimmed value can be read and adjusted as required.

Important notes:
  • Never write OADJ* registers while foreground calibration is underway
  • Never write OADJ* registers if CAL_BG and CAL_BGOS are set
  • If CAL_OS = 1 and CAL_BGOS = 0, only read OADJ* registers if FG_DONE = 1
  • If CAL_BG = 1 and CAL_BGOS = 1, only read OADJ* register if CAL_STOPPED = 1

7.6.1.47 Offset Adjustment for C-ADC and INA Register (address = 0x08E-0x08F) [reset = Undefined]

Figure 7-67 Offset Adjustment for C-ADC and INA Register (OADJ_C_INA)
15141312111098
RESERVEDOADJ_C_INA[11:8]
R/W-0000R/W
76543210
OADJ_C_INA[7:0]
R/W
Table 7-91 OADJ_C_INA Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/W0000RESERVED
11-0OADJ_C_INAR/WUndefinedOffset adjustment value for ADC1 (A-ADC) applied when ADC1 samples INA. The format is unsigned. After reset, the factory-trimmed value can be read and adjusted as required.

Important notes:
  • Never write OADJ* registers while foreground calibration is underway
  • Never write OADJ* registers if CAL_BG and CAL_BGOS are set
  • If CAL_OS = 1 and CAL_BGOS = 0, only read OADJ* registers if FG_DONE = 1
  • If CAL_BG = 1 and CAL_BGOS = 1, only read OADJ* register if CAL_STOPPED = 1

7.6.1.48 Offset Adjustment for C-ADC and INB Register (address = 0x090-0x091) [reset = Undefined]

Figure 7-68 Offset Adjustment for C-ADC and INB Register (OADJ_C_INB)
15141312111098
RESERVEDOADJ_C_INB[11:8]
R/W-0000R/W
76543210
OADJ_C_INB[7:0]
R/W
Table 7-92 OADJ_C_INB Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/W0000RESERVED
11-0OADJ_C_INBR/WUndefinedOffset adjustment value for ADC1 (A-ADC) applied when ADC1 samples INB. The format is unsigned. After reset, the factory-trimmed value can be read and adjusted as required.

Important notes:
  • Never write OADJ* registers while foreground calibration is underway
  • Never write OADJ* registers if CAL_BG and CAL_BGOS are set
  • If CAL_OS = 1 and CAL_BGOS = 0, only read OADJ* registers if FG_DONE = 1
  • If CAL_BG = 1 and CAL_BGOS = 1, only read OADJ* register if CAL_STOPPED = 1

7.6.1.49 Offset Adjustment for B-ADC and INA Register (address = 0x092-0x093) [reset = Undefined]

Figure 7-69 Offset Adjustment for B-ADC and INA Register (OADJ_B_INA)
15141312111098
RESERVEDOADJ_B_INA[11:8]
R/W-0000R/W
76543210
OADJ_B_INA[7:0]
R/W
Table 7-93 OADJ_B_INA Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/W0000RESERVED
11-0OADJ_B_INAR/WUndefinedOffset adjustment value for ADC2 (B-ADC) applied when ADC2 samples INA. The format is unsigned. After reset, the factory-trimmed value can be read and adjusted as required.

Important notes:
  • Never write OADJ* registers while foreground calibration is underway
  • Never write OADJ* registers if CAL_BG and CAL_BGOS are set
  • If CAL_OS = 1 and CAL_BGOS = 0, only read OADJ* registers if FG_DONE = 1
  • If CAL_BG = 1 and CAL_BGOS = 1, only read OADJ* register if CAL_STOPPED = 1

7.6.1.50 Offset Adjustment for B-ADC and INB Register (address = 0x094-0x095) [reset = Undefined]

Figure 7-70 Offset Adjustment for B-ADC and INB Register (OADJ_B_INB)
15141312111098
RESERVEDOADJ_B_INB[11:8]
R/W-0000R/W
76543210
OADJ_B_INB[7:0]
R/W
Table 7-94 OADJ_B_INB Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/W0000RESERVED
11-0OADJ_B_INBR/WUndefinedOffset adjustment value for ADC2 (B-ADC) applied when ADC2 samples INB. The format is unsigned. After reset, the factory-trimmed value can be read and adjusted as required.

Important notes:
  • Never write OADJ* registers while foreground calibration is underway
  • Never write OADJ* registers if CAL_BG and CAL_BGOS are set
  • If CAL_OS = 1 and CAL_BGOS=0, only read OADJ* registers if FG_DONE = 1
  • If CAL_BG = 1 and CAL_BGOS=1, only read OADJ* register if CAL_STOPPED = 1

7.6.1.51 Offset Filtering Control 0 Register (address = 0x097) [reset = 0x00]

Figure 7-71 Offset Filtering Control 0 Register (OSFILT0)
76543210
RESERVEDDC_RESTORE
R/W-0000 000R/W
Table 7-95 OSFILT0 Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0000 000RESERVED
0DC_RESTORER/W0When set, the offset filtering feature (enabled by CAL_OSFILT) filters only the offset mismatch across ADC banks and does not remove the frequency content near DC. When cleared, the feature filters all offsets from all banks, thus filtering all DC content in the signal; see the Offset Filtering section.

7.6.1.52 Offset Filtering Control 1 Register (address = 0x098) [reset = 0x33]

Figure 7-72 Offset Filtering Control 1 Register (OSFILT1)
76543210
OSFILT_BWOSFILT_SOAK
R/W-0011R/W-0011
Table 7-96 OSFILT1 Field Descriptions
BitFieldTypeResetDescription
7-4OSFILT_BWR/W0011This field adjusts the IIR filter bandwidth for the offset filtering feature (enabled by CAL_OSFILT). More bandwidth suppresses more flicker noise from the ADCs and reduces the offset spurs. Less bandwidth minimizes the impact of the filters on the mission mode signal.
OSFILT_BW: IIR coefficient: –3-dB bandwidth (single sided)
0: Reserved
1: 2-10 : 609e-9 × FDEVCLK
2: 2-11 : 305e-9 × FDEVCLK
3: 2-12 : 152e-9 × FDEVCLK
4: 2-13 : 76e-9 × FDEVCLK
5: 2-14 : 38e-9 × FDEVCLK
6-15: Reserved
3-0OSFILT_SOAKR/W0011This field adjusts the IIR soak time for the offset filtering feature. This field applies when offset filtering and background calibration are both enabled. This field determines how long the IIR filter is allowed to settle when first connected to an ADC after the ADC is calibrated. After the soak time completes, the ADC is placed online using the IIR filter. Set OSFILT_SOAK = OSFILT_BW.

7.6.1.53 ADC Bank Registers (0x100 to 0x15F)

Table 7-97 ADC Bank Registers
ADDRESSRESETACRONYMREGISTER NAMESECTION
0x100-0x101UndefinedRESERVEDRESERVED
0x102UndefinedB0_TIME_0Timing Adjustment for Bank 0 (0° Clock) RegisterSection 7.6.1.54
0x103UndefinedB0_TIME_90Timing Adjustment for Bank 0 (–90° Clock) RegisterSection 7.6.1.55
0x104-0x111UndefinedRESERVEDRESERVED
0x112UndefinedB1_TIME_0Timing Adjustment for Bank 1 (0° Clock) RegisterSection 7.6.1.56
0x113UndefinedB1_TIME_90Timing Adjustment for Bank 1 (–90° Clock) RegisterSection 7.6.1.57
0x114-0x121UndefinedRESERVEDRESERVED
0x122UndefinedB2_TIME_0Timing Adjustment for Bank 2 (0° Clock) RegisterSection 7.6.1.58
0x123UndefinedB2_TIME_90Timing Adjustment for Bank 2 (–90° Clock) RegisterSection 7.6.1.59
0x124-0x131UndefinedRESERVEDRESERVED
0x132UndefinedB3_TIME_0Timing Adjustment for Bank 3 (0° Clock) RegisterSection 7.6.1.60
0x133UndefinedB3_TIME_90Timing Adjustment for Bank 3 (–90° Clock) RegisterSection 7.6.1.61
0x134-0x141UndefinedRESERVEDRESERVED
0x142UndefinedB4_TIME_0Timing Adjustment for Bank 4 (0° Clock) RegisterSection 7.6.1.62
0x143UndefinedB4_TIME_90Timing Adjustment for Bank 4 (–90° Clock) RegisterSection 7.6.1.63
0x144-0x151UndefinedRESERVEDRESERVED
0x152UndefinedB5_TIME_0Timing Adjustment for Bank 5 (0° Clock) RegisterSection 7.6.1.64
0x153UndefinedB5_TIME_90Timing Adjustment for Bank 5 (–90° Clock) RegisterSection 7.6.1.65
0x154-0x15FUndefinedRESERVEDRESERVED

7.6.1.54 Timing Adjustment for Bank 0 (0° Clock) Register (address = 0x102) [reset = Undefined]

Figure 7-73 Timing Adjustment for Bank 0 (0° Clock) Register (B0_TIME_0)
76543210
B0_TIME_0
R/W
Table 7-98 B0_TIME_0 Field Descriptions
BitFieldTypeResetDescription
7-0B0_TIME_0R/WUndefinedTime adjustment for bank 0 (applied when the ADC is configured for 0° clock phase). After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.55 Timing Adjustment for Bank 0 (–90° Clock) Register (address = 0x103) [reset = Undefined]

Figure 7-74 Timing Adjustment for Bank 0 (–90° Clock) Register (B0_TIME_90)
76543210
B0_TIME_90
R/W
Table 7-99 B0_TIME_90 Field Descriptions
BitFieldTypeResetDescription
7-0B0_TIME_90R/WUndefinedTime adjustment for bank 0 (applied when the ADC is configured for –90° clock phase). After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.56 Timing Adjustment for Bank 1 (0° Clock) Register (address = 0x112) [reset = Undefined]

Figure 7-75 Timing Adjustment for Bank 1 (0° Clock) Register (B1_TIME_0)
76543210
B1_TIME_0
R/W
Table 7-100 B1_TIME_0 Field Descriptions
BitFieldTypeResetDescription
7-0B1_TIME_0R/WUndefinedTime adjustment for bank 1 (applied when the ADC is configured for 0° clock phase). After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.57 Timing Adjustment for Bank 1 (–90° Clock) Register (address = 0x113) [reset = Undefined]

Figure 7-76 Timing Adjustment for Bank 1 (–90° Clock) Register (B1_TIME_90)
76543210
B1_TIME_90
R/W
Table 7-101 B1_TIME_90 Field Descriptions
BitFieldTypeResetDescription
7-0B1_TIME_90R/WUndefinedTime adjustment for bank 1 (applied when the ADC is configured for –90° clock phase). After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.58 Timing Adjustment for Bank 2 (0° Clock) Register (address = 0x122) [reset = Undefined]

Figure 7-77 Timing Adjustment for Bank 2 (0° Clock) Register (B2_TIME_0)
76543210
B2_TIME_0
R/W
Table 7-102 B2_TIME_0 Field Descriptions
BitFieldTypeResetDescription
7-0B2_TIME_0R/WUndefinedTime adjustment for bank 2 (applied when the ADC is configured for 0° clock phase). After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.59 Timing Adjustment for Bank 2 (–90° Clock) Register (address = 0x123) [reset = Undefined]

Figure 7-78 Timing Adjustment for Bank 2 (–90° Clock) Register (B2_TIME_90)
76543210
B2_TIME_90
R/W
Table 7-103 B2_TIME_90 Field Descriptions
BitFieldTypeResetDescription
7-0B2_TIME_90R/WUndefinedTime adjustment for bank 2 (applied when the ADC is configured for –90° clock phase). After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.60 Timing Adjustment for Bank 3 (0° Clock) Register (address = 0x132) [reset = Undefined]

Figure 7-79 Timing Adjustment for Bank 3 (0° Clock) Register (B3_TIME_0)
76543210
B3_TIME_0
R/W
Table 7-104 B3_TIME_0 Field Descriptions
BitFieldTypeResetDescription
7-0B3_TIME_0R/WUndefinedTime adjustment for bank 3 (applied when the ADC is configured for 0° clock phase). After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.61 Timing Adjustment for Bank 3 (–90° Clock) Register (address = 0x133) [reset = Undefined]

Figure 7-80 Timing Adjustment for Bank 3 (–90° Clock) Register (B3_TIME_90)
76543210
B3_TIME_90
R/W
Table 7-105 B3_TIME_90 Field Descriptions
BitFieldTypeResetDescription
7-0B3_TIME_90R/WUndefinedTime adjustment for bank 3 (applied when the ADC is configured for –90° clock phase). After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.62 Timing Adjustment for Bank 4 (0° Clock) Register (address = 0x142) [reset = Undefined]

Figure 7-81 Timing Adjustment for Bank 4 (0° Clock) Register (B4_TIME_0)
76543210
B4_TIME_0
R/W
Table 7-106 B4_TIME_0 Field Descriptions
BitFieldTypeResetDescription
7-0B4_TIME_0R/WUndefinedTime adjustment for bank 4 (applied when the ADC is configured for 0° clock phase). After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.63 Timing Adjustment for Bank 4 (–90° Clock) Register (address = 0x143) [reset = Undefined]

Figure 7-82 Timing Adjustment for Bank 4 (–90° Clock) Register (B4_TIME_90)
76543210
B4_TIME_90
R/W
Table 7-107 B4_TIME_90 Field Descriptions
BitFieldTypeResetDescription
7-0B4_TIME_90R/WUndefinedTime adjustment for bank 4 (applied when the ADC is configured for –90° clock phase). After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.64 Timing Adjustment for Bank 5 (0° Clock) Register (address = 0x152) [reset = Undefined]

Figure 7-83 Timing Adjustment for Bank 5 (0° Clock) Register (B5_TIME_0)
76543210
B5_TIME_0
R/W
Table 7-108 B5_TIME_0 Field Descriptions
BitFieldTypeResetDescription
7-0B5_TIME_0R/WUndefinedTime adjustment for bank 5 (applied when the ADC is configured for 0° clock phase). After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.65 Timing Adjustment for Bank 5 (–90° Clock) Register (address = 0x153) [reset = Undefined]

Figure 7-84 Timing Adjustment for Bank 5 (–90° Clock) Register (B5_TIME_90)
76543210
B5_TIME_90
R/W
Table 7-109 B5_TIME_90 Field Descriptions
BitFieldTypeResetDescription
7-0B5_TIME_90R/WUndefinedTime adjustment for bank 5 (applied when the ADC is configured for –90° clock phase). After reset, the factory-trimmed value can be read and adjusted as required.

7.6.1.66 LSB Control Registers (0x160 to 0x1FF)

Table 7-110 LSB Control Registers
ADDRESSRESETACRONYMREGISTER NAMESECTION
0x1600x00ENC_LSBLSB Control Bit Output RegisterFigure 7-85
0x161-0x1FFUndefinedRESERVEDRESERVED

7.6.1.67 LSB Control Bit Output Register (address = 0x160) [reset = 0x00]

Figure 7-85 LSB Control Bit Output Register (ENC_LSB)
76543210
RESERVEDTIMESTAMP_EN
R/W-0000 000R/W-0
Table 7-111 ENC_LSB Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0000 000RESERVED
0TIMESTAMP_ENR/W0When set, the transport layer transmits the timestamp signal on the LSB of the output samples. Only supported in decimate-by-1 (DDC bypass) modes. TIMESTAMP_EN has priority over CAL_STATE_EN. TMSTP_RECV_EN must also be set high when using timestamp. The latency of the timestamp signal (through the entire device) matches the latency of the analog ADC inputs.

In 8-bit modes, the control bit is placed on the LSB of the 8-bit samples (leaving 7 bits of sample data). If the device is configured for 12-bit data, the control bit is placed on the LSB of the 12-bit data (leaving 11 bits of sample data).
The control bit enabled by this register is never advertised in the ILA (the CS field is 0 in the ILA).

7.6.1.68 JESD204B Registers (0x200 to 0x20F)

Table 7-112 JESD204B Registers
ADDRESSRESETACRONYMREGISTER NAMESECTION
0x2000x01JESD_ENJESD204B Enable RegisterSection 7.6.1.69
0x2010x02JMODEJESD204B Mode RegisterSection 7.6.1.70
0x2020x1FKM1JESD204B K Parameter RegisterSection 7.6.1.71
0x2030x01JSYNC_NJESD204B Manual SYNC Request RegisterSection 7.6.1.72
0x2040x02JCTRLJESD204B Control RegisterSection 7.6.1.73
0x2050x00JTESTJESD204B Test Pattern Control RegisterSection 7.6.1.74
0x2060x00DIDJESD204B DID Parameter RegisterSection 7.6.1.75
0x2070x00FCHARJESD204B Frame Character RegisterSection 7.6.1.76
0x208UndefinedJESD_STATUSJESD204B, System Status RegisterSection 7.6.1.77
0x2090x00PD_CHJESD204B Channel Power-DownSection 7.6.1.78
0x20A0x00JEXTRA_AJESD204B Extra Lane Enable (Link A)Section 7.6.1.79
0x20B0x00JEXTRA_BJESD204B Extra Lane Enable (Link B)Section 7.6.1.80
0x20C-0x20FUndefinedRESERVEDRESERVED

7.6.1.69 JESD204B Enable Register (address = 0x200) [reset = 0x01]

Figure 7-86 JESD204B Enable Register (JESD_EN)
76543210
RESERVEDJESD_EN
R/W-0000 000R/W-1
Table 7-113 JESD_EN Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0000 000RESERVED
0JESD_ENR/W10 : Disables JESD204B interface
1 : Enables JESD204B interface

Before altering other JESD204B registers, JESD_EN must be cleared. When JESD_EN is 0, the block is held in reset and the serializers are powered down. The clocks are gated off to save power. The LMFC counter is also held in reset, so SYSREF does not align the LMFC.
Always set CAL_EN before setting JESD_EN.
Always clear JESD_EN before clearing CAL_EN.

7.6.1.70 JESD204B Mode Register (address = 0x201) [reset = 0x02]

Figure 7-87 JESD204B Mode Register (JMODE)
76543210
RESERVEDJMODE
R/W-000R/W-0001 0
Table 7-114 JMODE Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W000RESERVED
4-0JMODER/W0001 0Specify the JESD204B output mode (including DDC decimation factor).

Only change this register when JESD_EN = 0 and CAL_EN = 0.

7.6.1.71 JESD204B K Parameter Register (address = 0x202) [reset = 0x1F]

Figure 7-88 JESD204B K Parameter Register (KM1)
76543210
RESERVEDKM1
R/W-000R/W-1111 1
Table 7-115 KM1 Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W000RESERVED
4-0KM1R/W1111 1K is the number of frames per multiframe and this register must be programmed as K-1. Depending on the JMODE setting, there are constraints on the legal values of K. (default: KM1 = 31, K = 32).

Only change this register when JESD_EN is 0.

7.6.1.72 JESD204B Manual SYNC Request Register (address = 0x203) [reset = 0x01]

Figure 7-89 JESD204B Manual SYNC Request Register (JSYNC_N)
76543210
RESERVEDJSYNC_N
R/W-0000 000R/W-1
Table 7-116 JSYNC_N Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0000 000RESERVED
0JSYNC_NR/W1Set this bit to 0 to request JESD204B synchronization (equivalent to the SYNCSE pin being asserted). For normal operation, leave this bit set to 1.

The JSYNC_N register can always generate a synchronization request, regardless of the SYNC_SEL register. However, if the selected sync pin is stuck low, the synchronization request cannot be de-asserted unless SYNC_SEL = 2 is programmed.

7.6.1.73 JESD204B Control Register (address = 0x204) [reset = 0x02]

Figure 7-90 JESD204B Control Register (JCTRL)
76543210
RESERVEDSYNC_SELSFORMATSCR
R/W-0000R/W-00R/W-1R/W-0
Table 7-117 JCTRL Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0000RESERVED
3-2SYNC_SELR/W000: Use the SYNCSE input for the SYNC~ function (default)
1: Use the TMSTP± differential input for the SYNC~ function; TMSTP_RECV_EN must also be set
2: Do not use any sync input signal (use software SYNC~ through JSYNC_N)
1SFORMATR/W1Output sample format for JESD204B samples.

0: Offset binary
1: Signed 2’s complement (default)
0SCRR/W00: Scrambler disabled (default)
1: Scrambler enabled

Only change this register when JESD_EN is 0.

7.6.1.74 JESD204B Test Pattern Control Register (address = 0x205) [reset = 0x00]

Figure 7-91 JESD204B Test Pattern Control Register (JTEST)
76543210
RESERVEDJTEST
R/W-0000R/W-0000
Table 7-118 JTEST Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0000RESERVED
3-0JTESTR/W00000: Test mode disabled; normal operation (default)
1: PRBS7 test mode
2: PRBS15 test mode
3: PRBS23 test mode
4: Ramp test mode
5: Transport layer test mode
6: D21.5 test mode
7: K28.5 test mode
8: Repeated ILA test mode
9: Modified RPAT test mode
10: Serial outputs held low
11: Serial outputs held high
12–15: Reserved

Only change this register when JESD_EN is 0.

7.6.1.75 JESD204B DID Parameter Register (address = 0x206) [reset = 0x00]

Figure 7-92 JESD204B DID Parameter Register (DID)
76543210
DID
R/W-0000 0000
Table 7-119 DID Field Descriptions
BitFieldTypeResetDescription
7-0DIDR/W0000 0000Specifies the device ID (DID) value that is transmitted during the second multiframe of the JESD204B ILA. Link A transmits DID, and link B transmits DID+1. Bit 0 is ignored and always returns 0 (if an odd number is programmed, that number is decremented to an even number).

Only change this register when JESD_EN is 0.

7.6.1.76 JESD204B Frame Character Register (address = 0x207) [reset = 0x00]

Figure 7-93 JESD204B Frame Character Register (FCHAR)
76543210
RESERVEDFCHAR
R/W-0000 00R/W-00
Table 7-120 FCHAR Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W0000 00RESERVED
1-0FCHARR/W00Specify which comma character is used to denote end-of-frame. This character is transmitted opportunistically (see the GUID-B32CD923-4B7D-4A5D-A66F-4A2A1CAEE56B.html#GUID-B32CD923-4B7D-4A5D-A66F-4A2A1CAEE56B section).

0: Use K28.7 (default, JESD204B compliant)
1: Use K28.1 (not JESD204B compliant)
2: Use K28.5 (not JESD204B compliant)
3: Reserved
When using a JESD204B receiver, always use FCHAR = 0. When using a general-purpose 8b, 10b receiver, the K28.7 character may cause issues. When K28.7 is combined with certain data characters, a false, misaligned comma character can result, and some receivers realign to the false comma. To avoid this condition, program FCHAR to 1 or 2.

Only change this register when JESD_EN is 0.

7.6.1.77 JESD204B, System Status Register (address = 0x208) [reset = Undefined]

Figure 7-94 JESD204B, System Status Register (JESD_STATUS)
76543210
RESERVEDLINK_UPSYNC_STATUSREALIGNEDALIGNEDPLL_LOCKEDRESERVED
RRRR/WR/WRR
Table 7-121 JESD_STATUS Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRUndefinedRESERVED
6LINK_UPRUndefinedWhen set, this bit indicates that the JESD204B link is up.
5SYNC_STATUSRUndefinedReturns the state of the JESD204B SYNC~ signal.

0: SYNC~ asserted
1: SYNC~ de-asserted
4REALIGNEDR/WUndefinedWhen high, this bit indicates that an internal digital clock, frame clock, or multiframe (LMFC) clock phase was realigned by SYSREF. Write a 1 to clear this bit.
3ALIGNEDR/WUndefinedWhen high, this bit indicates that the multiframe (LMFC) clock phase has been established by SYSREF. The first SYSREF event after enabling the JESD204B encoder will set this bit. Write a 1 to clear this bit.
2PLL_LOCKEDRUndefinedWhen high, this bit indicates that the PLL is locked.
1-0RESERVEDRUndefinedRESERVED

7.6.1.78 JESD204B Channel Power-Down Register (address = 0x209) [reset = 0x00]

Figure 7-95 JESD204B Channel Power-Down Register (PD_CH)
76543210
RESERVEDPD_BCHPD_ACH
R/W-0000 00R/W-0R/W-0
Table 7-122 PD_CH Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W0000 00RESERVED
1PD_BCHR/W0When set, the B ADC channel is powered down. The digital channels that are bound to the B ADC channel are also powered down (see the digital channel binding register).

Important notes:
Set JESD_EN = 0 before changing PD_CH.
To power-down both ADC channels, use MODE.
If both channels are powered down, then the entire JESD204B subsystem (including the PLL and LMFC) are powered down
If the selected JESD204B mode transmits A and B data on link A, and the B digital channel is disabled, link A remains operational, but the B-channel samples are undefined.
0PD_ACHR/W0When set, the A ADC channel is powered down. The digital channels that are bound to the A ADC channel are also powered down (digital channel binding register).

Important notes:
Set JESD_EN = 0 before changing PD_CH.
To power-down both ADC channels, use MODE.
If both channels are powered down, then the entire JESD204B subsystem (including the PLL and LMFC) are powered down
If the selected JESD204B mode transmits A and B data on link A, and the B digital channel is disabled, link A remains operational, but the B-channel samples are undefined.

7.6.1.79 JESD204B Extra Lane Enable (Link A) Register (address = 0x20A) [reset = 0x00]

Figure 7-96 JESD204B Extra Lane Enable (Link A) Register (JEXTRA_A)
76543210
EXTRA_LANE_AEXTRA_SER_A
R/W-0000 000R/W-0
Table 7-123 JESD204B Extra Lane Enable (Link A) Field Descriptions
BitFieldTypeResetDescription
7-1EXTRA_LANE_AR/W0000 000Program these register bits to enable extra lanes (even if the selected JMODE does not require the lanes to be enabled). EXTRA_LANE_A(n) enables An (n = 1 to 7). This register enables the link layer clocks for the affected lanes. To also enable the extra serializes set EXTRA_SER_A = 1.
0EXTRA_SER_AR/W00: Only the link layer clocks for extra lanes are enabled.
1: Serializers for extra lanes are also enabled. Use this mode to transmit data from the extra lanes.
Important notes:
Only change this register when JESD_EN = 0.
The bit-rate and mode of the extra lanes are set by the JMODE and JTEST parameters.
This register does not override the PD_CH register, so ensure that the link is enabled to use this feature.
To enable serializer n, the lower number lanes 0 to n-1 must also be enabled, otherwise serializer n does not receive a clock.

7.6.1.80 JESD204B Extra Lane Enable (Link B) Register (address = 0x20B) [reset = 0x00]

Figure 7-97 JESD204B Extra Lane Enable (Link B) Register (JEXTRA_B)
76543210
EXTRA_LANE_BEXTRA_SER_B
R/W-0000 000R/W-0
Table 7-124 JESD204B Extra Lane Enable (Link B) Field Descriptions
BitFieldTypeResetDescription
7-1EXTRA_LANE_BR/W0000 000Program these register bits to enable extra lanes (even if the selected JMODE does not require the lanes to be enabled). EXTRA_LANE_B(n) enables Bn (n = 1 to 7). This register enables the link layer clocks for the affected lanes. To also enable the extra serializes set EXTRA_SER_B = 1.
0EXTRA_SER_BR/W00: Only the link layer clocks for extra lanes are enabled.
1: Serializers for extra lanes are also enabled. Use this mode to transmit data from the extra lanes.
Important notes:
Only change this register when JESD_EN = 0.
The bit-rate and mode of the extra lanes are set by the JMODE and JTEST parameters.
This register does not override the PD_CH register, so ensure that the link is enabled to use this feature.
To enable serializer n, the lower number lanes 0 to n-1 must also be enabled, otherwise serializer n does not receive a clock.

7.6.1.81 Digital Down Converter Registers (0x210-0x2AF)

Table 7-125 Digital Down Converter and Overrange Registers
ADDRESSRESETACRONYMREGISTER NAMESECTION
0x2100x00DDC_CFGDDC Configuration RegisterSection 7.6.1.82
0x2110xF2OVR_T0Overrange Threshold 0 RegisterSection 7.6.1.83
0x2120xABOVR_T1Overrange Threshold 1 RegisterSection 7.6.1.84
0x2130x07OVR_CFGOverrange Configuration RegisterSection 7.6.1.85
0x2140x00CMODEDDC Configuration Preset Mode RegisterSection 7.6.1.86
0x2150x00CSELDDC Configuration Preset Select RegisterSection 7.6.1.87
0x2160x02DIG_BINDDigital Channel Binding RegisterSection 7.6.1.88
0x217-0x2180x0000NCO_RDIVRational NCO Reference Divisor RegisterSection 7.6.1.89
0x2190x02NCO_SYNCNCO Synchronization RegisterSection 7.6.1.90
0x21A-0x21FUndefinedRESERVEDRESERVED
0x220-0x2230xC0000000FREQA0NCO Frequency (DDC A Preset 0)Section 7.6.1.91
0x224-0x2250x0000PHASEA0NCO Phase (DDC A Preset 0)Section 7.6.1.92
0x226-0x227UndefinedRESERVEDRESERVED
0x228-0x22B0xC0000000FREQA1NCO Frequency (DDC A Preset 1)Section 7.6.1.91
0x22C-0x22D0x0000PHASEA1NCO Phase (DDC A Preset 1)Section 7.6.1.92
0x22E-0x22FUndefinedRESERVEDRESERVED
0x230-0x2330xC0000000FREQA2NCO Frequency (DDC A Preset 2)Section 7.6.1.91
0x234-0x2350x0000PHASEA2NCO Phase (DDC A Preset 2)Section 7.6.1.92
0x236-0x237UndefinedRESERVEDRESERVED
0x238-0x23B0xC0000000FREQA3NCO Frequency (DDC A Preset 3)Section 7.6.1.91
0x23C-0x23D0x0000PHASEA3NCO Phase (DDC A Preset 3)Section 7.6.1.92
0x23E-0x23FUndefinedRESERVEDRESERVED
0x240-0x2430xC0000000FREQB0NCO Frequency (DDC B Preset 0)Section 7.6.1.91
0x244-0x2450x0000PHASEB0NCO Phase (DDC B Preset 0)Section 7.6.1.92
0x246-0x247UndefinedRESERVEDRESERVED
0x248-0x24B0xC0000000FREQB1NCO Frequency (DDC B Preset 1)Section 7.6.1.91
0x24C-0x24D0x0000PHASEB1NCO Phase (DDC B Preset 1)Section 7.6.1.92
0x24E-0x24FUndefinedRESERVEDRESERVED
0x250-0x2530xC0000000FREQB2NCO Frequency (DDC B Preset 2)Section 7.6.1.91
0x254-0x2550x0000PHASEB2NCO Phase (DDC B Preset 2)Section 7.6.1.92
0x256-0x257UndefinedRESERVEDRESERVED
0x258-0x25B0xC0000000FREQB3NCO Frequency (DDC B Preset 3)Section 7.6.1.91
0x25C-0x25D0x0000PHASEB3NCO Phase (DDC B Preset 3)Section 7.6.1.92
0x25E-0x296UndefinedRESERVEDRESERVED
0x297UndefinedSPIN_IDSpin Identification ValueSection 7.6.1.93
0x298-0x2AFUndefinedRESERVEDRESERVED

7.6.1.82 DDC Configuration Register (address = 0x210) [reset = 0x00]

Figure 7-98 DDC Configuration Register (DDC_CFG)
76543210
RESERVEDD4_AP87D2_HIGH_PASSINVERT_SPECTRUMBOOST
R/W-0000R/W-0R/W-0R/W-0R/W-0
Table 7-126 DDC_CFG Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0000RESERVED
3D4_AP87R/W00: Decimate-by-4 mode uses 80% alias protection, > 80-dB suppression
1: Decimate-by-4 mode uses 87.5% alias protection, > 60-dB suppression
2D2_HIGH_PASSR/W00: Decimate-by-2 mode uses a low-pass filter
1: Decimate-by-2 mode uses a high-pass filter. Decimating the high-pass signal causes spectral inversion. This inversion can be undone by setting INVERT_SPECTRUM.
1INVERT_SPECTRUMR/W00: No inversion applied to output spectrum
1: Output spectrum is inverted

This register only applies when the DDC is enabled and is producing a real output (not complex). The spectrum is inverted by mixing the signal with FSOUT / 2 (for example, invert all odd samples).
0BOOSTR/W0DDC gain control. Only applies to DDC modes with complex decimation.

0: Final filter has 0-dB gain (default)
1: Final filter has 6.02-dB gain. Only use this setting when certain that the negative image of the input signal is filtered out by the DDC, otherwise digital clipping may occur.

7.6.1.83 Overrange Threshold 0 Register (address = 0x211) [reset = 0xF2]

Figure 7-99 Overrange Threshold 0 Register (OVR_T0)
76543210
OVR_T0
R/W-1111 0010
Table 7-127 OVR_T0 Field Descriptions
BitFieldTypeResetDescription
7-0OVR_T0R/W1111 0010Overrange threshold 0. This parameter defines the absolute sample level that causes control bit 0 to be set. The detection level in dBFS (peak) is:
20log10(OVR_T0 / 256)
Default: 0xF2 = 242 → –0.5 dBFS.

7.6.1.84 Overrange Threshold 1 Register (address = 0x212) [reset = 0xAB]

Figure 7-100 Overrange Threshold 1 Register (OVR_T1)
76543210
OVR_T1
R/W-1010 1011
Table 7-128 OVR_T1 Field Descriptions
BitFieldTypeResetDescription
7-0OVR_T1R/W1010 1011Overrange threshold 1. This parameter defines the absolute sample level that causes control bit 1 to be set. The detection level in dBFS (peak) is:
20log10(OVR_T1 / 256)
Default: 0xAB = 171 → –3.5 dBFS.

7.6.1.85 Overrange Configuration Register (address = 0x213) [reset = 0x07]

Figure 7-101 Overrange Configuration Register (OVR_CFG)
76543210
RESERVEDOVR_ENOVR_N
R/W-0000R/W-0R/W-111
Table 7-129 OVR_CFG Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0000 0RESERVED
3OVR_ENR/W0Enables overrange status output pins when set high. The ORA0, ORA1, ORB0, and ORB1 outputs are held low when OVR_EN is set low. This register only effects the overrange output pins (ORxx) and not the overrange status embedded in the data samples.
2-0OVR_N#SLAS9699974R/W111Program this register to adjust the pulse extension for the ORA0, ORA1 and ORB0, ORB1 outputs. The minimum pulse duration of the overrange outputs is 8 × 2OVR_N DEVCLK cycles. Incrementing this field doubles the monitoring period.
Changing the OVR_N setting while JESD_EN=1 may cause the phase of the monitoring period to change.

7.6.1.86 DDC Configuration Preset Mode Register (address = 0x214) [reset = 0x00]

Figure 7-102 DDC Configuration Preset Mode Register (CMODE)
76543210
RESERVEDCMODE
R/W-0000 00R/W-00
Table 7-130 CMODE Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W0000 00RESERVED
1-0CMODER/W00The NCO frequency and phase for DDC A are set by the FREQAx and PHASEAx registers and the NCO frequency and phase for DDC B are set by the FREQBx and PHASEBx registers, where x is the configuration preset (0 through 3).

0: Use CSEL register to select the active NCO configuration preset for DDC A and DDC B
1: Use NCOA[1:0] pins to select the active NCO configuration preset for DDC A and use NCOB[1:0] pins to select the active NCO configuration preset for DDC B
2: Use NCOA[1:0] pins to select the active NCO configuration preset for both DDC A and DDC B
3: Reserved

7.6.1.87 DDC Configuration Preset Select Register (address = 0x215) [reset = 0x00]

Figure 7-103 DDC Configuration Preset Select Register (CSEL)
76543210
RESERVEDCSELBCSELA
R/W-0000R/W-00R/W-00
Table 7-131 CSEL Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0000RESERVED
3-2CSELBR/W00When CMODE = 0, this register is used to select the active NCO configuration preset for DDC B.
1-0CSELAR/W00When CMODE = 0, this register is used to select the active NCO configuration preset for DDC A.

Example: If CSELA = 0, then FREQA0 and PHASEA0 are the active settings. If CSELA = 1, then FREQA1 and PHASEA1 are the active settings.

7.6.1.88 Digital Channel Binding Register (address = 0x216) [reset = 0x02]

Figure 7-104 Digital Channel Binding Register (DIG_BIND)
76543210
RESERVEDDIG_BIND_BDIG_BIND_A
R/W-0000 00R/W-1R/W-0
Table 7-132 DIG_BIND Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W0000 00RESERVED
1DIG_BIND_BR/W0Digital channel B input select:

0: Digital channel B receives data from ADC channel A
1: Digital channel B receives data from ADC channel B (default)
0DIG_BIND_AR/W0Digital channel A input select:

0: Digital channel A receives data from ADC channel A (default)
1: Digital channel A receives data from ADC channel B

When using single-channel mode, always use the default setting for DIG_BIND or the device does not work.
Set JESD_EN = 0 and CAL_EN = 0 before changing DIG_BIND.
The DIG_BIND setting is combined with PD_ACH, PD_BCH to determine if a digital channel is powered down. Each digital channel (and link) is powered down when the ADC channel it is bound to is powered down (by PD_ACH, PD_BCH).

7.6.1.89 Rational NCO Reference Divisor Register (address = 0x217 to 0x218) [reset = 0x0000]

Figure 7-105 Rational NCO Reference Divisor Register (NCO_RDIV)
15141312111098
NCO_RDIV[15:8]
R/W-0000 0000
76543210
NCO_RDIV[7:0]
R/W-0000 0000
Table 7-133 NCO_RDIV Field Descriptions
BitFieldTypeResetDescription
15-0NCO_RDIVR/W0x0000hSometimes the 32-bit NCO frequency word does not provide the desired frequency step size and can only approximate the desired frequency. This condition results in a frequency error. Use this register to eliminate the frequency error. This register is used for all configuration presets; see the GUID-DAD74652-5075-453B-A43F-4897FAE9D3C6.html#GUID-DAD74652-5075-453B-A43F-4897FAE9D3C6 section.

7.6.1.90 NCO Synchronization Register (address = 0x219) [reset = 0x02]

Figure 7-106 NCO Synchronization Register (NCO_SYNC)
76543210
RESERVEDNCO_SYNC_ILANCO_SYNC_NEXT
R/W-0000 00R/W-1R/W-0
Table 7-134 NCO_SYNC Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W0000 00RESERVED
1NCO_SYNC_ILAR/W0When this bit is set, the NCO phase is initialized by the LMFC edge that starts the ILA sequence (default).
0NCO_SYNC_NEXTR/W0After writing a 0 and then a 1 to this bit, the next SYSREF rising edge initializes the NCO phase. When the NCO phase is initialized by SYSREF, the NCO does not reinitialize on future SYSREF edges unless a 0 and a 1 is written to this bit again.

Follow these steps to align the NCO in multiple parts:
  • Ensure the device is powered up, JESD_EN is set, and the device clock is running.
  • Ensure that SYSREF is disabled (not toggling).
  • Program NCO_SYNC_ILA = 0 on all devices.
  • Write NCO_SYNC_NEXT = 0 on all devices.
  • Write NCO_SYNC_NEXT = 1 on all devices. NCO sync is armed.
  • Instruct the SYSREF source to generate 1 or more SYSREF pulses.
  • All devices initialize their NCO using the first SYSREF rising edge.

7.6.1.91 NCO Frequency (DDC A or DDC B and Preset x) Register (address = see Table 7-125) [reset = see Table 7-125]

Figure 7-107 NCO Frequency (DDC A or DDC B and Preset x) Register (FREQAx or FREQBx)
3130292827262524
FREQAx[31:24] or FREQBx[31:24]
R/W-0xC0
2322212019181716
FREQAx[23:16] or FREQBx[23:16]
R/W-0x00
15141312111098
FREQAx[15:8] or FREQBx[15:8]
R/W-0x00
76543210
FREQAx[7:0] or FREQBx[7:0]
R/W-0x00
Table 7-135 FREQAx or FREQBx Field Descriptions
BitFieldTypeResetDescription
31-0FREQAx or FREQBxR/WSee Table 7-125Changing this register after the JESD204B interface is running results in non-deterministic NCO phase. If deterministic phase is required, the JESD204B interface must be re-initialized after changing this register. This register can be interpreted as signed or unsigned. When interpreted as signed (2's complement) the NCO frequency is between –fS / 2 to fS / 2. When interpreted as unsigned the NCO frequency is between 0 and fS.

7.6.1.92 NCO Phase (DDC A or DDC B and Preset x) Register (address = see Table 7-125) [reset = see Table 7-125]

Figure 7-108 NCO Phase (DDC A or DDC B and Preset x) Register (PHASEAx or PHASEBx)
15141312111098
PHASEAx[15:8] or PHASEBx[15:8]
R/W-0x00
76543210
PHASEAx[7:0] or PHASEBx[7:0]
R/W-0x00
Table 7-136 PHASEAx or PHASEBx Field Descriptions
BitFieldTypeResetDescription
15-0PHASEAx or PHASEBxR/WSee Table 7-125This value is MSB-justified into a 32-bit field and then added to the phase accumulator. This register can be interpreted as signed or unsigned; see the GUID-ACADE568-F64F-4441-87B7-1244A8DC1132.html#GUID-ACADE568-F64F-4441-87B7-1244A8DC1132 section.

7.6.1.93 Spin Identification Register (address = 0x297) [reset = Undefined]

Figure 7-109 Spin Identification Register (SPIN_ID)
76543210
RESERVEDSPIN_ID
R-000R
Table 7-137 SPIN_ID Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR000RESERVED
4-0SPIN_IDR5Spin identification value.
5 : ADC12DJ3200QML-SP