12ビット、RF サンプリング A/D コンバータ (ADC)" />

JAJSGI4B November   2018  – March 2021 ADC12DJ3200QML-SP

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
      2. 7.3.2 ADC Core
        1. 7.3.2.1 ADC Theory of Operation
        2. 7.3.2.2 ADC Core Calibration
        3. 7.3.2.3 ADC Overrange Detection
        4. 7.3.2.4 Code Error Rate (CER)
      3. 7.3.3 Timestamp
      4. 7.3.4 Clocking
        1. 7.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.4.3.2 Automatic SYSREF Calibration
      5. 7.3.5 Digital Down Converters (Dual-Channel Mode Only)
        1. 7.3.5.1 Numerically-Controlled Oscillator and Complex Mixer
          1. 7.3.5.1.1 NCO Fast Frequency Hopping (FFH)
          2. 7.3.5.1.2 NCO Selection
          3. 7.3.5.1.3 Basic NCO Frequency Setting Mode
          4. 7.3.5.1.4 Rational NCO Frequency Setting Mode
          5. 7.3.5.1.5 NCO Phase Offset Setting
          6. 7.3.5.1.6 NCO Phase Synchronization
        2. 7.3.5.2 Decimation Filters
        3. 7.3.5.3 Output Data Format
        4. 7.3.5.4 Decimation Settings
          1. 7.3.5.4.1 Decimation Factor
          2. 7.3.5.4.2 DDC Gain Boost
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 Transport Layer
        2. 7.3.6.2 Scrambler
        3. 7.3.6.3 Link Layer
          1. 7.3.6.3.1 Code Group Synchronization (CGS)
          2. 7.3.6.3.2 Initial Lane Alignment Sequence (ILAS)
          3. 7.3.6.3.3 8b, 10b Encoding
          4. 7.3.6.3.4 Frame and Multiframe Monitoring
        4. 7.3.6.4 Physical Layer
          1. 7.3.6.4.1 SerDes Pre-Emphasis
        5. 7.3.6.5 JESD204B Enable
        6. 7.3.6.6 Multi-Device Synchronization and Deterministic Latency
        7. 7.3.6.7 Operation in Subclass 0 Systems
      7. 7.3.7 Alarm Monitoring
        1. 7.3.7.1 NCO Upset Detection
        2. 7.3.7.2 Clock Upset Detection
      8. 7.3.8 Temperature Monitoring Diode
      9. 7.3.9 Analog Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 JESD204B Modes
        1. 7.4.3.1 JESD204B Output Data Formats
        2. 7.4.3.2 Dual DDC and Redundant Data Mode
      4. 7.4.4 Power-Down Modes
      5. 7.4.5 Test Modes
        1. 7.4.5.1 Serializer Test-Mode Details
        2. 7.4.5.2 PRBS Test Modes
        3. 7.4.5.3 Ramp Test Mode
        4. 7.4.5.4 Short and Long Transport Test Mode
          1. 7.4.5.4.1 Short Transport Test Pattern
          2. 7.4.5.4.2 Long Transport Test Pattern
        5. 7.4.5.5 D21.5 Test Mode
        6. 7.4.5.6 K28.5 Test Mode
        7. 7.4.5.7 Repeated ILA Test Mode
        8. 7.4.5.8 Modified RPAT Test Mode
      6. 7.4.6 Calibration Modes and Trimming
        1. 7.4.6.1 Foreground Calibration Mode
        2. 7.4.6.2 Background Calibration Mode
        3. 7.4.6.3 Low-Power Background Calibration (LPBG) Mode
      7. 7.4.7 Offset Calibration
      8. 7.4.8 Trimming
      9. 7.4.9 Offset Filtering
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
      2. 7.6.2 SYSREF Calibration Registers (0x2B0 to 0x2BF)
      3. 7.6.3 Alarm Registers (0x2C0 to 0x2C2)
  8. Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Analog Inputs
      2. 8.1.2 Analog Input Bandwidth
      3. 8.1.3 Clocking
      4. 8.1.4 Radiation Environment Recommendations
        1. 8.1.4.1 Single Event Latch-Up (SEL)
        2. 8.1.4.2 Single Event Functional Interrupt (SEFI)
        3. 8.1.4.3 Single Event Upset (SEU)
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 RF Input Signal Path
        2. 8.2.2.2 Calculating Values of AC-Coupling Capacitors
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
      1.      Power Supply Recommendations
        1. 9.1 Power Sequencing
  9. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
      1.      Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • ZMX|196
  • NWE|196
サーマルパッド・メカニカル・データ
発注情報

ADC Overrange Detection

To make sure that system gain management has the quickest possible response time, a low-latency configurable overrange function is included. The overrange function works by monitoring the converted 12-bit samples at the ADC to quickly detect if the ADC is near saturation or already in an overrange condition. The absolute value of the upper 8 bits of the ADC data are checked against two programmable thresholds, OVR_T0 and OVR_T1. These thresholds apply to both channel A and channel B in dual-channel mode. Table 7-1 lists how an ADC sample is converted to an absolute value for a comparison of the thresholds.

Table 7-1 Conversion of ADC Sample for Overrange Comparison
ADC SAMPLE
(Offset Binary)
ADC SAMPLE
(2's Complement)
ABSOLUTE VALUEUPPER 8 BITS USED FOR COMPARISON
1111 1111 1111 (4095)0111 1111 1111 (+2047)111 1111 1111 (2047)1111 1111 (255)
1111 1111 0000 (4080)0111 1111 0000 (+2032)111 1111 0000 (2032)1111 1110 (254)
1000 0000 0000 (2048)0000 0000 0000 (0)000 0000 0000 (0)0000 0000 (0)
0000 0001 0000 (16)1000 0001 0000 (–2032)111 1111 0000 (2032)1111 1110 (254)
0000 0000 0000 (0)1000 0000 0000 (–2048)111 1111 1111 (2047)1111 1111 (255)

If the upper 8 bits of the absolute value equal or exceed the OVR_T0 or OVR_T1 thresholds during the monitoring period, then the overrange bit associated with the threshold is set to 1, otherwise the overrange bit is 0. In dual-channel mode, the overrange status can be monitored on the ORA0 and ORA1 pins for channel A and the ORB0 and ORB1 pins for channel B, where ORx0 corresponds to the OVR_T0 threshold and ORx1 corresponds to the OVR_T1 threshold. In single-channel mode, the overrange status for the OVR_T0 threshold is determined by monitoring both the ORA0 and ORB0 outputs and the OVR_T1 threshold is determined by monitoring both ORA1 and ORB1 outputs. In single-channel mode, the two outputs for each threshold must be OR'd together to determine whether an overrange condition occurred. OVR_N can be used to set the output pulse duration from the last overrange event. Table 7-2 lists the overrange pulse lengths for the various OVR_N settings (see the overrange configuration register). In decimation modes (only in the JMODEs where CS = 1 in Table 7-18), the overrange status is also embedded into the output data samples. For complex decimation modes, the OVR_T0 threshold status is embedded as the LSB along with the upper 15 bits of every complex I sample and the OVR_T1 threshold status is embedded as the LSB along with the upper 15 bits of every complex Q sample. For real decimation modes, the OVR_T0 threshold status is embedded as the LSB of every even-numbered sample and the OVR_T1 threshold status is embedded as the LSB of every odd-numbered sample. Table 7-3 lists the outputs, related data samples, threshold settings, and the monitoring period equation. The embedded overrange bit goes high if the associated channel exceeds the associated overrange threshold within the monitoring period set by OVR_N. Use Table 7-3 to calculate the monitoring period.

Table 7-2 Overrange Monitoring Period for the ORA0, ORA1, ORB0, and ORB1 Outputs
OVR_NOVERRANGE PULSE LENGTH SINCE LAST OVERRANGE EVENT (DEVCLK Cycles)
08
116
232
364
4128
5256
6512
71024
Table 7-3 Threshold and Monitoring Period for Embedded Overrange Indicators in Dual-Channel Decimation Modes
OVERRANGE INDICATORASSOCIATED THRESHOLDDECIMATION TYPEOVERRANGE STATUS EMBEDDED INMONITORING PERIOD
(ADC Samples)
ORA0OVR_T0Real decimation (JMODE 9)Channel A even-numbered samples2OVR_N+1(1)
Complex down-conversion (JMODE 10-16, except JMODE 12)Channel A in-phase (I) samples2OVR_N(1)
ORA1OVR_T1Real decimation (JMODE 9)Channel A odd-numbered samples2OVR_N+1(1)
Complex down-conversion (JMODE 10-16, except JMODE 12)Channel A quadrature (Q) samples2OVR_N(1)
ORB0OVR_T0Real decimation (JMODE 9)Channel B even-numbered samples2OVR_N+1(1)
Complex down-conversion (JMODE 10-16, except JMODE 12)Channel B in-phase (I) samples2OVR_N(1)
ORB1OVR_T1Real decimation (JMODE 9)Channel B odd-numbered samples2OVR_N+1(1)
Complex down-conversion (JMODE 10-16, except JMODE 12)Channel B quadrature (Q) samples2OVR_N(1)
OVR_N is the monitoring period register setting.

Typically, the OVR_T0 threshold can be set near the full-scale value (228 for example). When the threshold is triggered, a typical system can turn down the system gain to avoid clipping. The OVR_T1 threshold can be set much lower. For example, the OVR_T1 threshold can be set to 64 (peak input voltage of −12 dBFS). If the input signal is strong, the OVR_T1 threshold is tripped occasionally. If the input is quite weak, the threshold is never tripped. The downstream logic device monitors the OVR_T1 bit. If OVR_T1 stays low for an extended period of time, then the system gain can be increased until the threshold is occasionally tripped (meaning the peak level of the signal is above −12 dBFS).