12ビット、RF サンプリング A/D コンバータ (ADC)" />

JAJSGI4B November   2018  – March 2021 ADC12DJ3200QML-SP

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
      2. 7.3.2 ADC Core
        1. 7.3.2.1 ADC Theory of Operation
        2. 7.3.2.2 ADC Core Calibration
        3. 7.3.2.3 ADC Overrange Detection
        4. 7.3.2.4 Code Error Rate (CER)
      3. 7.3.3 Timestamp
      4. 7.3.4 Clocking
        1. 7.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.4.3.2 Automatic SYSREF Calibration
      5. 7.3.5 Digital Down Converters (Dual-Channel Mode Only)
        1. 7.3.5.1 Numerically-Controlled Oscillator and Complex Mixer
          1. 7.3.5.1.1 NCO Fast Frequency Hopping (FFH)
          2. 7.3.5.1.2 NCO Selection
          3. 7.3.5.1.3 Basic NCO Frequency Setting Mode
          4. 7.3.5.1.4 Rational NCO Frequency Setting Mode
          5. 7.3.5.1.5 NCO Phase Offset Setting
          6. 7.3.5.1.6 NCO Phase Synchronization
        2. 7.3.5.2 Decimation Filters
        3. 7.3.5.3 Output Data Format
        4. 7.3.5.4 Decimation Settings
          1. 7.3.5.4.1 Decimation Factor
          2. 7.3.5.4.2 DDC Gain Boost
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 Transport Layer
        2. 7.3.6.2 Scrambler
        3. 7.3.6.3 Link Layer
          1. 7.3.6.3.1 Code Group Synchronization (CGS)
          2. 7.3.6.3.2 Initial Lane Alignment Sequence (ILAS)
          3. 7.3.6.3.3 8b, 10b Encoding
          4. 7.3.6.3.4 Frame and Multiframe Monitoring
        4. 7.3.6.4 Physical Layer
          1. 7.3.6.4.1 SerDes Pre-Emphasis
        5. 7.3.6.5 JESD204B Enable
        6. 7.3.6.6 Multi-Device Synchronization and Deterministic Latency
        7. 7.3.6.7 Operation in Subclass 0 Systems
      7. 7.3.7 Alarm Monitoring
        1. 7.3.7.1 NCO Upset Detection
        2. 7.3.7.2 Clock Upset Detection
      8. 7.3.8 Temperature Monitoring Diode
      9. 7.3.9 Analog Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 JESD204B Modes
        1. 7.4.3.1 JESD204B Output Data Formats
        2. 7.4.3.2 Dual DDC and Redundant Data Mode
      4. 7.4.4 Power-Down Modes
      5. 7.4.5 Test Modes
        1. 7.4.5.1 Serializer Test-Mode Details
        2. 7.4.5.2 PRBS Test Modes
        3. 7.4.5.3 Ramp Test Mode
        4. 7.4.5.4 Short and Long Transport Test Mode
          1. 7.4.5.4.1 Short Transport Test Pattern
          2. 7.4.5.4.2 Long Transport Test Pattern
        5. 7.4.5.5 D21.5 Test Mode
        6. 7.4.5.6 K28.5 Test Mode
        7. 7.4.5.7 Repeated ILA Test Mode
        8. 7.4.5.8 Modified RPAT Test Mode
      6. 7.4.6 Calibration Modes and Trimming
        1. 7.4.6.1 Foreground Calibration Mode
        2. 7.4.6.2 Background Calibration Mode
        3. 7.4.6.3 Low-Power Background Calibration (LPBG) Mode
      7. 7.4.7 Offset Calibration
      8. 7.4.8 Trimming
      9. 7.4.9 Offset Filtering
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
      2. 7.6.2 SYSREF Calibration Registers (0x2B0 to 0x2BF)
      3. 7.6.3 Alarm Registers (0x2C0 to 0x2C2)
  8. Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Analog Inputs
      2. 8.1.2 Analog Input Bandwidth
      3. 8.1.3 Clocking
      4. 8.1.4 Radiation Environment Recommendations
        1. 8.1.4.1 Single Event Latch-Up (SEL)
        2. 8.1.4.2 Single Event Functional Interrupt (SEFI)
        3. 8.1.4.3 Single Event Upset (SEU)
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 RF Input Signal Path
        2. 8.2.2.2 Calculating Values of AC-Coupling Capacitors
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
      1.      Power Supply Recommendations
        1. 9.1 Power Sequencing
  9. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
      1.      Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • ZMX|196
  • NWE|196
サーマルパッド・メカニカル・データ
発注情報

Timing Requirements

SUBGROUP(1)MINNOMMAXUNIT
DEVICE (Sampling) CLOCK (CLK+, CLK–)
fCLKInput clock frequency (CLK+, CLK–), both single-channel and dual-channel modes(2)Maximum input clock frequency[4, 5, 6]3200MHz
Minimum input clock frequency800MHz
SYSREF (SYSREF+, SYSREF–)
tCLKInput clock period (CLK+, CLK–), both single-channel and dual-channel modes(2)Maximum input clock frequency[4, 5, 6]312.5ps
Minimum input clock frequency1250ps
tINV(SYSREF)Duration of invalid SYSREF capture region of CLK± period, indicating setup or hold time violation, as measured by the SYSREF_POS status register(3)48ps
tINV(TEMP)Drift of invalid SYSREF capture region over temperature, a positive number indicates a shift toward the MSB of the SYSREF_POS register0ps/°C
tINV(VA11)Drift of invalid SYSREF capture region over the VA11 supply voltage, a positive number indicates a shift toward the MSB of the SYSREF_POS register0.36ps/mV
tSTEP(SP)Delay of the SYSREF_POS LSBSYSREF_ZOOM = 077ps
SYSREF_ZOOM = 124
t(PH_SYS)Minimum SYSREF± assertion duration after a SYSREF± rising edge event4ns
t(PL_SYS)Minimum SYSREF± de-assertion duration after a SYSREF± falling edge event4ns
JESD204B SYNC TIMING ( SYNCSE OR TMSTP±)
tH( SYNCSE)Minimum hold time from multiframe boundary (SYSREF rising edge captured high) to de-assertion of JESD204B SYNC signal ( SYNCSE if SYNC_SEL = 0 or TMSTP± if SYNC_SEL = 1) for NCO synchronization (NCO_SYNC_ILA = 1)JMODE = 0, 2, 4, 6, 10, 13 or 1521tCLK cycles
JMODE = 1, 3, 5, 7, 9, 11, 14 or 1617
JMODE = 12, 17 or 189
tSU( SYNCSE)Minimum setup time from de-assertion of JESD204B SYNC signal ( SYNCSE if SYNC_SEL = 0 or TMSTP± if SYNC_SEL = 1) to multiframe boundary (SYSREF rising edge captured high) for NCO synchronization (NCO_SYNC_ILA = 1)JMODE = 0, 2, 4, 6, 10, 13 or 15–2tCLK cycles
JMODE = 1, 3, 5, 7, 9, 11, 14 or 162
JMODE = 12, 17 or 1810
t( SYNCSE)SYNCSE minimum assertion time to trigger link resynchronization4Frames
SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS)
fCLK(SCLK)Serial clock frequency[4, 5, 6]0.015.625MHz
t(PH)Serial clock high value pulse duration[4, 5, 6]32ns
t(PL)Serial clock low value pulse duration[4, 5, 6]32ns
tSU( SCS)Setup time from SCS to rising edge of SCLK[4, 5, 6]25ns
tH( SCS)Hold time from rising edge of SCLK to SCS[4, 5, 6]3ns
tSU(SDI)Setup time from SDI to rising edge of SCLK[4, 5, 6]25ns
tH(SDI)Hold time from rising edge of SCLK to SDI[4, 5, 6]3ns
For subgroup definitions, please see Table 6-1.
Unless functionally limited to a smaller range in Table 7-18 based on the programmed JMODE.
Use SYSREF_POS to select an optimal SYSREF_SEL value for SYSREF capture, see SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) for more information on SYSREF windowing. The invalid region, specified by tINV(SYSREF), indicates the portion of the CLK± period (tCLK), as measured by SYSREF_SEL, that may result in a setup and hold violation. Verify that the timing skew between SYSREF± and CLK± over system operating conditions from the nominal conditions (that used to find optimal SYSREF_SEL) does not result in the invalid region occurring at the selected SYSREF_SEL position in SYSREF_POS, otherwise a temperature dependent SYSREF_SEL selection may be needed to track the skew between CLK± and SYSREF±.