JAJSW71 February   2025 ADC3683-EP , ADC3683-SEP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics - ADC3683
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Input Bandwidth
        2. 7.3.1.2 Analog Front End Design
          1. 7.3.1.2.1 Sampling Glitch Filter Design
          2. 7.3.1.2.2 Analog Input Termination and DC Bias
            1. 7.3.1.2.2.1 AC-Coupling
            2. 7.3.1.2.2.2 DC-Coupling
        3. 7.3.1.3 Auto-Zero Feature
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Single Ended vs Differential Clock Input
        2. 7.3.2.2 Signal Acquisition Time Adjust
      3. 7.3.3 Voltage Reference
        1. 7.3.3.1 Internal voltage reference
        2. 7.3.3.2 External voltage reference (VREF)
        3. 7.3.3.3 External voltage reference with internal buffer (REFBUF/CTRL)
      4. 7.3.4 Digital Down Converter
        1. 7.3.4.1 DDC MUX
        2. 7.3.4.2 Digital Filter Operation
        3. 7.3.4.3 FS/4 Mixing with Real Output
        4. 7.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 7.3.4.5 Decimation Filter
        6. 7.3.4.6 SYNC
        7. 7.3.4.7 Output Formatting with Decimation
      5. 7.3.5 Digital Data Path and Interface
        1. 7.3.5.1 Data Path Overview
        2. 7.3.5.2 Output Scrambler
        3. 7.3.5.3 Output Bit Mapper
          1. 7.3.5.3.1 2-Wire Mode
          2. 7.3.5.3.2 1-Wire Mode
          3. 7.3.5.3.3 ½-Wire Mode
        4. 7.3.5.4 Device Configuration Steps
          1. 7.3.5.4.1 Configuration Example
        5. 7.3.5.5 Output Data Format
      6. 7.3.6 Test Pattern
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Power Down Options
      3. 7.4.3 Digital Channel Averaging
    5. 7.5 Programming
      1. 7.5.1 Configuration using PINs only
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Sampling Clock
        3. 8.2.2.3 Voltage Reference
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Register Initialization During Operation
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Register Map
    1. 9.1 Detailed Register Description
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RSB|40
サーマルパッド・メカニカル・データ
発注情報

5.9 Typical Characteristics - ADC3683

Typical values at TA = 25 °C, ADC sampling rate = 65MSPS, AIN = –1dBFS differential input, AVDD = IOVDD = 1.8V, external 1.6V voltage reference, unless otherwise noted.

ADC3683-SEP ADC3683-EP Single Tone FFT at FIN = 1 MHz
SNR = 84.2dBFS, SFDR = 81dBc, Non HD23 = 101dBFS
Figure 5-1 Single Tone FFT at FIN = 1 MHz
ADC3683-SEP ADC3683-EP Single Tone FFT at FIN = 5MHz, AIN = -20dBFS
SNR = 84.8dBFS, SFDR = 81dBc, Non HD23 = 103dBFS
Figure 5-3 Single Tone FFT at FIN = 5MHz, AIN = -20dBFS
ADC3683-SEP ADC3683-EP Single Tone FFT at FIN = 40MHz
SNR = 81.1dBFS, SFDR = 84dBc, Non HD23 = 95dBFS
Figure 5-5 Single Tone FFT at FIN = 40MHz
ADC3683-SEP ADC3683-EP Single Tone FFT at FIN = 100MHz
SNR = 75.1dBFS, SFDR = 75dBc, Non HD23 = 93dBFS
Figure 5-7 Single Tone FFT at FIN = 100MHz
ADC3683-SEP ADC3683-EP Two Tone FFT at FIN = 10/12MHz
AIN = -20dBFS/tone, IMD3 = 95dBc
Figure 5-9 Two Tone FFT at FIN = 10/12MHz
ADC3683-SEP ADC3683-EP AC Performance vs Input Frequency
Figure 5-11 AC Performance vs Input Frequency
ADC3683-SEP ADC3683-EP AC Performance vs Input Amplitude
FIN = 5MHz
Figure 5-13 AC Performance vs Input Amplitude
ADC3683-SEP ADC3683-EP AC Performance vs Clock Amplitude
Figure 5-15 AC Performance vs Clock Amplitude
ADC3683-SEP ADC3683-EP AC Performance vs AVDD
FIN = 5MHz
Figure 5-17 AC Performance vs AVDD
ADC3683-SEP ADC3683-EP AC Performance vs Clock Duty Cycle
FIN = 5MHz
Figure 5-19 AC Performance vs Clock Duty Cycle
ADC3683-SEP ADC3683-EP INL vs Code
FIN = 5MHz
Figure 5-21 INL vs Code
ADC3683-SEP ADC3683-EP DC Offset Histogram
Figure 5-23 DC Offset Histogram
ADC3683-SEP ADC3683-EP Current vs Sampling Rate
FIN = 5MHz, DDC Bypass
Figure 5-25 Current vs Sampling Rate
ADC3683-SEP ADC3683-EP IIOVDD Current vs Output Interface
FIN = 5MHz, Complex Decimation by 32
Figure 5-27 IIOVDD Current vs Output Interface
ADC3683-SEP ADC3683-EP Single Tone FFT at FIN = 5MHz
SNR = 83.8dBFS, SFDR = 89dBc, Non HD23 = 99dBFS
Figure 5-2 Single Tone FFT at FIN = 5MHz
ADC3683-SEP ADC3683-EP Single Tone FFT at FIN = 10MHz
SNR = 83.8dBFS, SFDR = 92dBc, Non HD23 = 98dBFS
Figure 5-4 Single Tone FFT at FIN = 10MHz
ADC3683-SEP ADC3683-EP Single Tone FFT at FIN = 64MHz
SNR = 77.3dBFS, SFDR = 86dBc, Non HD23 = 92dBFS
Figure 5-6 Single Tone FFT at FIN = 64MHz
ADC3683-SEP ADC3683-EP Two Tone FFT at FIN = 10/12MHz
AIN = -7dBFS/tone, IMD3 = 88dBc
Figure 5-8 Two Tone FFT at FIN = 10/12MHz
ADC3683-SEP ADC3683-EP Two Tone FFT at FIN = 40/45MHz
AIN = -7dBFS/tone, IMD3 = 83dBc
Figure 5-10 Two Tone FFT at FIN = 40/45MHz
ADC3683-SEP ADC3683-EP ENOB vs Input Frequency
Figure 5-12 ENOB vs Input Frequency
ADC3683-SEP ADC3683-EP AC Performance vs Sampling Rate
FIN = 5MHz
Figure 5-14 AC Performance vs Sampling Rate
ADC3683-SEP ADC3683-EP AC Performance vs Clock Amplitude
Single ended clock input
Figure 5-16 AC Performance vs Clock Amplitude
ADC3683-SEP ADC3683-EP AC Performance vs VCM vs Temperature
FIN = 5MHz
Figure 5-18 AC Performance vs VCM vs Temperature
ADC3683-SEP ADC3683-EP Isolation vs Input Frequency
Figure 5-20 Isolation vs Input Frequency
ADC3683-SEP ADC3683-EP DNL vs Code
FIN = 5MHz
Figure 5-22 DNL vs Code
ADC3683-SEP ADC3683-EP Pulse Response
FIN = 1MHz
Figure 5-24 Pulse Response
ADC3683-SEP ADC3683-EP IIOVDD Current vs Decimation
FIN = 5MHz, 2-wire
Figure 5-26 IIOVDD Current vs Decimation