JAJSW71 February   2025 ADC3683-EP , ADC3683-SEP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics - ADC3683
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Input Bandwidth
        2. 7.3.1.2 Analog Front End Design
          1. 7.3.1.2.1 Sampling Glitch Filter Design
          2. 7.3.1.2.2 Analog Input Termination and DC Bias
            1. 7.3.1.2.2.1 AC-Coupling
            2. 7.3.1.2.2.2 DC-Coupling
        3. 7.3.1.3 Auto-Zero Feature
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Single Ended vs Differential Clock Input
        2. 7.3.2.2 Signal Acquisition Time Adjust
      3. 7.3.3 Voltage Reference
        1. 7.3.3.1 Internal voltage reference
        2. 7.3.3.2 External voltage reference (VREF)
        3. 7.3.3.3 External voltage reference with internal buffer (REFBUF/CTRL)
      4. 7.3.4 Digital Down Converter
        1. 7.3.4.1 DDC MUX
        2. 7.3.4.2 Digital Filter Operation
        3. 7.3.4.3 FS/4 Mixing with Real Output
        4. 7.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 7.3.4.5 Decimation Filter
        6. 7.3.4.6 SYNC
        7. 7.3.4.7 Output Formatting with Decimation
      5. 7.3.5 Digital Data Path and Interface
        1. 7.3.5.1 Data Path Overview
        2. 7.3.5.2 Output Scrambler
        3. 7.3.5.3 Output Bit Mapper
          1. 7.3.5.3.1 2-Wire Mode
          2. 7.3.5.3.2 1-Wire Mode
          3. 7.3.5.3.3 ½-Wire Mode
        4. 7.3.5.4 Device Configuration Steps
          1. 7.3.5.4.1 Configuration Example
        5. 7.3.5.5 Output Data Format
      6. 7.3.6 Test Pattern
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Power Down Options
      3. 7.4.3 Digital Channel Averaging
    5. 7.5 Programming
      1. 7.5.1 Configuration using PINs only
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Sampling Clock
        3. 8.2.2.3 Voltage Reference
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Register Initialization During Operation
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Register Map
    1. 9.1 Detailed Register Description
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RSB|40
サーマルパッド・メカニカル・データ
発注情報

7.3.4.7 Output Formatting with Decimation

When using decimation, the digital output data is formatted as shown in Figure 7-38 (complex decimation) and Figure 7-39 (real decimation).The output format is illustrated for 18-bit output resolution.

ADC3683-SEP ADC3683-EP Output Data Format in Complex Decimation (18-bit Output Resolution)Figure 7-38 Output Data Format in Complex Decimation (18-bit Output Resolution)

Table 7-4 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK frequencies based on output resolution (R), number of SLVDS lanes (L) and complex decimation setting (N).

Tthe table shows an actual lane rate example for the 2-, 1- and 1/2-wire interface, 18-bit output resolution and complex decimation by 4.

Table 7-4 Serial LVDS Lane Rate Examples with Complex Decimation and 18-bit Output Resolution
DECIMATION SETTINGADC SAMPLING RATEOUTPUT RESOLUTION# of WIRESFCLKDCLKIN, DCLKDA/B0,1
NFSRLFS / N[DA/B0,1] / 2FS x 2 x R / L / N
465MSPS18216.25MHz146.25 MHz292.5 MHz
1292.5 MHz585 MHz
55MSPS1/213.75MHz495 MHz990 MHz
ADC3683-SEP ADC3683-EP Output Data Format in Real Decimation (18-bit Output Resolution)Figure 7-39 Output Data Format in Real Decimation (18-bit Output Resolution)

Table 7-5 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK frequencies based on output resolution (R), number of SLVDS lanes (L) and real decimation setting (M).

The table shows an actual lane rate example for the 2-, 1- and 1/2-wire interface, 18-bit output resolution and real decimation by 4.

Table 7-5 Serial LVDS Lane Rate Examples with Real Decimation and 18-bit Output Resolution
DECIMATION SETTINGADC SAMPLING RATEOUTPUT RESOLUTION# of WIRESFCLKDCLKIN, DCLKDA/B0,1
MFSRLFS / M / 2 (L = 2)
FS / M (L = 1, 1/2)		[DA/B0,1] / 2FS x R / L / M
465MSPS1828.125MHz73.125 MHz146.25 MHz
116.25MHz146.25 MHz292.5 MHz
1/2292.5 MHz585 MHz