JAJSL70A February   2021  – January 2024 BQ25730

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 概要 (続き)
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics(BQ25730)
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power-Up Sequence
      2. 8.3.2  Two-Level Battery Discharge Current Limit
      3. 8.3.3  Fast Role Swap Feature
      4. 8.3.4  CHRG_OK Indicator
      5. 8.3.5  Input and Charge Current Sensing
      6. 8.3.6  Input Voltage and Current Limit Setup
      7. 8.3.7  Battery Cell Configuration
      8. 8.3.8  Device HIZ State
      9. 8.3.9  USB On-The-Go (OTG)
      10. 8.3.10 Converter Operation
      11. 8.3.11 Inductance Detection Through IADPT Pin
      12. 8.3.12 Converter Compensation
      13. 8.3.13 Continuous Conduction Mode (CCM)
      14. 8.3.14 Pulse Frequency Modulation (PFM)
      15. 8.3.15 Switching Frequency and Dithering Feature
      16. 8.3.16 Current and Power Monitor
        1. 8.3.16.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 8.3.16.2 High-Accuracy Power Sense Amplifier (PSYS)
      17. 8.3.17 Input Source Dynamic Power Management
      18. 8.3.18 Input Current Optimizer (ICO)
      19. 8.3.19 Two-Level Adapter Current Limit (Peak Power Mode)
      20. 8.3.20 Processor Hot Indication
        1. 8.3.20.1 PROCHOT During Low Power Mode
        2. 8.3.20.2 PROCHOT Status
      21. 8.3.21 Device Protection
        1. 8.3.21.1 Watchdog Timer
        2. 8.3.21.2 Input Overvoltage Protection (ACOV)
        3. 8.3.21.3 Input Overcurrent Protection (ACOC)
        4. 8.3.21.4 System Overvoltage Protection (SYSOVP)
        5. 8.3.21.5 Battery Overvoltage Protection (BATOVP)
        6. 8.3.21.6 Battery Discharge Overcurrent Protection (BATOC)
        7. 8.3.21.7 Battery Short Protection (BATSP)
        8. 8.3.21.8 System Undervoltage Lockout (VSYS_UVP) and Hiccup Mode
        9. 8.3.21.9 Thermal Shutdown (TSHUT)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forward Mode
        1. 8.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 8.4.1.2 Battery Charging
      2. 8.4.2 USB On-The-Go
      3. 8.4.3 Pass Through Mode (PTM)-Patented Technology
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
        1. 8.5.1.1 Timing Diagrams
        2. 8.5.1.2 Data Validity
        3. 8.5.1.3 START and STOP Conditions
        4. 8.5.1.4 Byte Format
        5. 8.5.1.5 Acknowledge (ACK) and Not Acknowledge (NACK)
        6. 8.5.1.6 Target Address and Data Direction Bit
        7. 8.5.1.7 Single Read and Write
        8. 8.5.1.8 Multi-Read and Multi-Write
        9. 8.5.1.9 Write 2-Byte I2C Commands
    6. 8.6 Register Map
      1. 8.6.1  ChargeOption0 Register (I2C address = 01/00h) [reset = E70Eh]
      2. 8.6.2  ChargeCurrent Register (I2C address = 03/02h) [reset = 0000h]
        1. 8.6.2.1 Battery Pre-Charge Current Clamp
      3. 8.6.3  ChargeVoltage Register (I2C address = 05/04h) [reset value based on CELL_BATPRESZ pin setting]
      4. 8.6.4  ChargerStatus Register (I2C address = 21/20h) [reset = 0000h]
      5. 8.6.5  ProchotStatus Register (I2C address = 23/22h) [reset = B800h]
      6. 8.6.6  IIN_DPM Register (I2C address = 25/24h) [reset = 4100h]
      7. 8.6.7  ADCVBUS/PSYS Register (I2C address = 27/26h)
      8. 8.6.8  ADCIBAT Register (I2C address = 29/28h)
      9. 8.6.9  ADCIIN/CMPIN Register (I2C address = 2B/2Ah)
      10. 8.6.10 ADCVSYS/VBAT Register (I2C address = 2D/2Ch)
      11. 8.6.11 ChargeOption1 Register (I2C address = 31/30h) [reset = 3F00h]
      12. 8.6.12 ChargeOption2 Register (I2C address = 33/32h) [reset = 00B7]
      13. 8.6.13 ChargeOption3 Register (I2C address = 35/34h) [reset = 0434h]
      14. 8.6.14 ProchotOption0 Register (I2C address = 37/36h) [reset = 4A81h(2S~5s) 4A09(1S)]
      15. 8.6.15 ProchotOption1 Register (I2C address = 39/38h) [reset = 41A0h]
      16. 8.6.16 ADCOption Register (I2C address = 3B/3Ah) [reset = 2000h]
      17. 8.6.17 ChargeOption4 Register (I2C address = 3D/3Ch) [reset = 0048h]
      18. 8.6.18 Vmin Active Protection Register (I2C address = 3F/3Eh) [reset = 006Ch(2s~5s)/0004h(1S)]
      19. 8.6.19 OTGVoltage Register (I2C address = 07/06h) [reset = 09C4h]
      20. 8.6.20 OTGCurrent Register (I2C address = 09/08h) [reset = 3C00h]
      21. 8.6.21 InputVoltage(VINDPM) Register (I2C address = 0B/0Ah) [reset =VBUS-1.28V]
      22. 8.6.22 VSYS_MIN Register (I2C address = 0D/0Ch) [reset value based on CELL_BATPRESZ pin setting]
      23. 8.6.23 IIN_HOST Register (I2C address = 0F/0Eh) [reset = 2000h]
      24. 8.6.24 ID Registers
        1. 8.6.24.1 ManufactureID Register (I2C address = 2Eh) [reset = 40h]
        2. 8.6.24.2 Device ID (DeviceAddress) Register (I2C address = 2Fh) [reset = D5h]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Snubber and Filter for Voltage Spike Damping
        2. 9.2.2.2 ACP-ACN Input Filter
        3. 9.2.2.3 Inductor Selection
        4. 9.2.2.4 Input Capacitor
        5. 9.2.2.5 Output Capacitor
        6. 9.2.2.6 Power MOSFETs Selection
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Layout Example Reference Top View
      2. 11.2.2 Inner Layer Layout and Routing Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.6.23 IIN_HOST Register (I2C address = 0F/0Eh) [reset = 2000h]

To set the nominal or typical input current limit based on the adapter rated current. Write a 7-bit IIN_HOST register command using the data format listed below.

When using a 10-mΩ sense resistor (RSNS_RAC=0b), the charger provides a nominal input-current limit range of 50 mA to 6350 mA, with 50-mA resolution. The upper boundary is implemented through DAC clamp, writing value higher than limitation will be neglected. The lower boundary is implemented through 50-mA offset at code 0. Note this offset is only applied to code 0, not applied to other codes. The default nominal input current limit is 3.25 A. Upon adapter removal, the input current limit is reset to the default value of 3.25 A.

When using a 5-mΩ sense resistor (RSNS_RAC=1b) referring to Section 8.3.5, the input-current limit range can be found under certain IADPT pin, EN_FAST_5MOHM bit status. The lower boundary is implemented through 100-mA offset at code 0. Note this offset is only applied to code 0, not applied to other codes. The default current limit is 3.2 A. Due to the USB current setting requirement, the register setting specifies the maximum current instead of the typical current. Upon adapter removal, the nominal input current limit is reset to the default value of 3.2 A.

To set the maximum input current limit based on adapter rated current. Additional 100-mA (10-mΩ sense resistor)/200-mA (5-mΩ sense resistor) offset should be added based on above nominal input current limit to obtain the maximum input current limit.

The ACP and ACN pins are used to sense RAC with the default value of 5 mΩ. For a 10-mΩ sense resistor, a larger sense voltage is given and a better regulation accuracy, but at the cost of higher conduction loss.

Instead of using the internal IIN_DPM loop, the user can build up an external input current regulation loop and have the feedback signal on the ILIM_HIZ pin.

In order to disable ILIM_HIZ pin, the host can write EN_EXTILIM=0b to disable ILIM_HIZ pin, or pull ILIM_HIZ pin above 4.0 V.

Figure 8-38 IIN_HOST Register (I2C address = 0F/0Eh) [reset = 4100h]
7 6 5 4 3 2 1 0
Reserved Input Current set by host, bit 6 Input Current set by host, bit 5 Input Current set by host, bit 4 Input Current set by host, bit 3 Input Current set by host, bit 2 Input Current set by host, bit 1 Input Current set by host, bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-52 IIN_HOST Register With 5-mΩ Sense Resistor (I2C address = 0Fh) Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
7 Reserved R/W 0b

Not used. 1 = invalid write.
6 Input Current set by host, bit 6 R/W 0b

0 = Adds 0 mA of input current.

1 = Adds 6400 mA of input current.
5 Input Current set by host, bit 5 R/W 1b

0 = Adds 0 mA of input current.

1 = Adds 3200 mA of input current.
4 Input Current set by host, bit 4 R/W 0b

0 = Adds 0 mA of input current.

1 = Adds 1600 mA of input current.
3 Input Current set by host, bit 3 R/W 0b

0 = Adds 0 mA of input current.

1 = Adds 800 mA of input current.
2 Input Current set by host, bit 2 R/W 0b

0 = Adds 0 mA of input current.

1 = Adds 400 mA of input current.
1 Input Current set by host, bit 1 R/W 0b

0 = Adds 0 mA of input current.

1 = Adds 200 mA of input current.
0 Input Current set by host, bit 0 R/W 0b

0 = Adds 0 mA of input current.

1 = Adds 100 mA of input current.
Table 8-53 IIN_HOST Register With 5-mΩ Sense Resistor (I2C address = 0Eh) Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
7-0 Reserved R 00000000b

Not used. Value Ignored.