JAJSH94 April 2019 BQ79606A-Q1
PRODUCTION DATA.
KEY: ADDR = Address; R = Read; W = Write; R/W = Read/Write; NVM = Non-volatile memory (OTP): 'Various' indicates that the value is set in the factory and is not consistent device to device.
Reserved bits that are located between 0x100 to 0x2E2 are not implemented in the design. Any writes to these bits are ignored. Reads to these bits always return '0'. However the reserved bits located between 0x00 to 0xC7 are implemented and is part of CRC calculation. The user should not write them. Spare bits are implemented in the design, but do not perform a function. These bits are read/write as normal, but do not influence any behaviors, but can be included in CRC calculation depending on the location (as indicated in the summary register table).
General Note on Command Buffers: There are three command buffers (one for UART, COMH, and COML) which assemble frames as they are received. The command buffers check for IERR, SOF, BERR and CRC. If a frame is valid and passes all those checks, then it gets sent to the command processor, which then checks TXDIS and UNEXP.
Register details are shown using the format shown in Table 33
REGISTERNAME Register Address: REGISTER ADDRESS | |||||||
B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
Bit Name | Bit Name | Bit Name | Bit Name | Bit Name | Bit Name | Bit Name | Bit Name |
Bit 7 Hardware Default | Bit 6 Hardware Default | Bit 5 Hardware Default | Bit 4 Hardware Default | Bit 3 Hardware Default | Bit 2 Hardware Default | Bit 1 Hardware Default | Bit 0 Hardware Default |
R-Read, W-Write, RW-Read/Write | R-Read, W-Write, RW-Read/Write | R-Read, W-Write, RW-Read/Write | R-Read, W-Write, RW-Read/Write | R-Read, W-Write, RW-Read/Write | R-Read, W-Write, RW-Read/Write | R-Read, W-Write, RW-Read/Write | R-Read, W-Write, RW-Read/Write |
Bit Name [bit number] | Bit Description | ||||||
Bit Name [bit number] | Bit Description |