JAJSH94 April 2019 BQ79606A-Q1
PRODUCTION DATA.
COMM_UART_RR_STAT2 Register Address: 0x27C | |||||||
B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
VALIDL[7] | VALIDL[6] | VALIDL[5] | VALIDL[4] | VALIDL[3] | VALIDL[2] | VALIDL[1] | VALIDL[0] |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
R | R | R | R | R | R | R | R |
VALIDL[7:0] | High byte of the valid command counter for received response frames from the UART interface. Counter saturates when COMM_UART_RC_STAT1[VALIDH] and COMM_UART_RC_STAT1[VALIDL] reach 0xFFFF. The COMM_UART_*_STAT* registers are updated and the counters are reset when the COMM_UART_RC_STAT3 register is read to ensure all counter data refers to the same period of time. |