JAJSH94 April 2019 BQ79606A-Q1
PRODUCTION DATA.
CELL_ADC_CONF1 Register Address: 0x24 | |||||||
B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
SPARE | DR[1] | DR[0] | ADC_FREQ[1] | ADC_FREQ[0] | FILSHIFT[2] | FILSHIFT[1] | FILSHIFT[0] |
0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 |
RW | RW | RW | RW | RW | RW | RW | RW |
SPARE | Spare | ||||||
DR[1:0] | Sets decimation ratio for ADC (applies to all cell and DIETEMP ADCs)
00: 32 01: 64 10: 128 11: 256 |
||||||
ADC_FREQ[1:0] | Selects ADC sample frequency (applies to all cell and DIETEMP ADCs)
00: 1 MHz 01: Reserved (1MHz operation) 10: Reserved (1MHz operation) 11: Reserved (1MHz operation) |
||||||
FILSHIFT[2:0] | Selects first order ADC lowpass filter corner frequency (frequencies only valid for ADC_CONF1[ADC_FREQ]=00 and ADC_CONF1[DR]=11). See" Digital RC Corner Frequencies" table for other DR settings in "Single Pole Digital Filter" section
000: 180.1 Hz 001: 83.1 Hz 010: 40.1 Hz 011: 19.7 HZ 100: 9.8 Hz 101: 4.9 Hz 110: 2.4 Hz 111: 1.2 Hz |