JAJSRI9A October   2023  – March 2024 LM51772

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 概要 (続き)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Buck-Boost Control Scheme
        1. 8.3.1.1 Buck Mode
        2. 8.3.1.2 Boost Mode
        3. 8.3.1.3 Buck-Boost Mode
      2. 8.3.2  Power Save Mode
      3. 8.3.3  Programmable Conduction Mode PCM
      4. 8.3.4  Reference System
        1. 8.3.4.1 VIO LDO and nRST-PIN
      5. 8.3.5  Supply Voltage Selection – VMAX Switch and Selection Logic
      6. 8.3.6  Enable and Undervoltage Lockout
        1. 8.3.6.1 UVLO
        2. 8.3.6.2 VDET Comparator
      7. 8.3.7  Internal VCC Regulator
        1. 8.3.7.1 VCC1 Regulator
        2. 8.3.7.2 VCC2 Regulator
      8. 8.3.8  Error Amplifier and Control
        1. 8.3.8.1 Output Voltage Regulation
        2. 8.3.8.2 Internal Output Voltage Regulation
        3. 8.3.8.3 Dynamic Voltage Scaling
      9. 8.3.9  Short Circuit - Hiccup Protection
      10. 8.3.10 Current Monitor/Limiter
        1. 8.3.10.1 Overview
        2. 8.3.10.2 Output Current Limitation
        3. 8.3.10.3 Output Current Monitor
      11. 8.3.11 Oscillator Frequency Selection
      12. 8.3.12 Frequency Synchronization
      13. 8.3.13 Output Voltage Tracking
        1. 8.3.13.1 Analog Voltage Tracking
        2. 8.3.13.2 Digital Voltage Tracking
      14. 8.3.14 Slope Compensation
      15. 8.3.15 Configurable Soft Start
      16. 8.3.16 Drive Pin
      17. 8.3.17 Dual Random Spread Spectrum – DRSS
      18. 8.3.18 Gate Driver
      19. 8.3.19 Cable Drop Compensation (CDC)
      20. 8.3.20 CFG-pin and R2D Interface
      21. 8.3.21 Advanced Monitoring Features
        1. 8.3.21.1  Overview
        2. 8.3.21.2  BUSY
        3. 8.3.21.3  OFF
        4. 8.3.21.4  VOUT
        5. 8.3.21.5  IOUT
        6. 8.3.21.6  INPUT
        7. 8.3.21.7  TEMPERATURE
        8. 8.3.21.8  CML
        9. 8.3.21.9  OTHER
        10. 8.3.21.10 ILIM_OP
        11. 8.3.21.11 nFLT/nINT Pin Output
        12. 8.3.21.12 Status Byte
      22. 8.3.22 Protection Features
        1. 8.3.22.1  Thermal Shutdown (TSD)
        2. 8.3.22.2  Over Current Protection
        3. 8.3.22.3  Output Over Voltage Protection 1 (OVP1)
        4. 8.3.22.4  Output Over Voltage Protection 2 (OVP2)
        5. 8.3.22.5  Input Voltage Protection (IVP)
        6. 8.3.22.6  Input Voltage Regulation (IVR)
        7. 8.3.22.7  Power Good
        8. 8.3.22.8  Boot-Strap Under Voltage Protection
        9. 8.3.22.9  Boot-strap Over Voltage Clamp
        10. 8.3.22.10 CRC - CHECK
    4. 8.4 Device Functional Modes
      1. 8.4.1 Overview
      2. 8.4.2 Logic State Description
    5. 8.5 Programming
      1. 8.5.1 I2C Bus Operation
      2. 8.5.2 Clock Stretching
      3. 8.5.3 Data Transfer Formats
      4. 8.5.4 Single READ from a Defined Register Address
      5. 8.5.5 Sequential READ Starting from a Defined Register Address
      6. 8.5.6 Single WRITE to a Defined Register Address
      7. 8.5.7 Sequential WRITE Starting at a Defined Register Address
  10. 9 LM51772 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Custom Design with WEBENCH Tools
        2. 10.2.2.2  Frequency
        3. 10.2.2.3  Feedback Divider
        4. 10.2.2.4  Inductor and Current Sense Resistor Selection
        5. 10.2.2.5  Output Capacitor
        6. 10.2.2.6  Input Capacitor
        7. 10.2.2.7  Slope Compensation
        8. 10.2.2.8  UVLO Divider
        9. 10.2.2.9  Soft-Start Capacitor
        10. 10.2.2.10 MOSFETs QH1 and QL1
        11. 10.2.2.11 MOSFETs QH2 and QL2
        12. 10.2.2.12 Loop Compensation
        13. 10.2.2.13 External Component Selection
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 Power Stage Layout
        2. 10.4.1.2 Gate Driver Layout
        3. 10.4.1.3 Controller Layout
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.5 Supply Voltage Selection – VMAX Switch and Selection Logic

There are two pins to supply the LM51772 internal voltage regulators. Due to the internal supply voltage selection circuit, the device can reduce the power dissipation by ensuring a seamless operation at low input or output voltages as well as in transient operating conditions like an output short. The VMAX switch selects the pin with the lower voltage from the VIN or BIAS pin once the voltage on both is above the switch-over threshold (VT(VCC, SUP)). If one pin voltage is lower than the threshold, the other supply pin is selected. And if both pins are lower than the switch-over threshold, the higher voltage of VIN or BIAS is selected as supply. The following are common configurations for the supply pins:

  • The VIN pin is connected to the supply voltage. The BIAS pin is connected to VO. During start-up, that is as long as the output voltage is not higher than the supply switch-over threshold, the VIN supplies the internal regulators. Once VO is high enough, the supply current comes from the BIAS pin.
  • Both the VIN pin and the BIAS pin are connected together to the input supply voltage. This configuration is often used in applications where the input supply voltage is usually lower or equal than the output voltage. As the BIAS pin is connected to the input voltage, the device has the full current capability of the internal regulators at low input voltages for start-up.
  • The VIN is connected to the input supply voltage and the BIAS pin is connected to an auxiliary supply (for example, an existing 12V DC/DC converter). This configuration is commonly used at high voltage applications on the input and output voltages where the power dissipation over the integrated linear regulators must be further minimized.

GUID-20210901-SS0I-P9TL-RW9D-MQQJTFFLWMGD-low.gif

Figure 8-9 VMAX Supply Scenario 1
GUID-20210901-SS0I-J4KG-XXX5-PPCKMQZQGLS9-low.gifFigure 8-10 VMAX Supply Scenario 2

GUID-20210901-SS0I-GGS5-4SZL-XP0G46LTFSR1-low.gif

Figure 8-11 VMAX Supply Scenario 3

The VMAX does not directly select the highest voltage between the two supply pins BIAS and VIN. To achieve a minimum of power losses over the LDO the VMAX logic will decide what voltage is the closest one to the target supply VT(VCC,SUP) . The Table 8-1 gives an overview for the selection conditions:

Table 8-1 VMAX selection truth table
V(BIAS)V(VIN)VMAX supply
X> VT+(VCC,SUP) && < V(BIAS)VIN-PIN
> VT+(VCC,SUP) && < V(VIN)XBIAS-PIN
< VT-(VCC,SUP)XVIN-PIN
X< VT-(VCC,SUP)BIAS-PIN
> VT+(VCC,SUP) && > V(VIN)> VT+(VCC,SUP)VIN-PIN
> VT+(VCC,SUP)> VT+(VCC,SUP) && > V(BIAS)BIAS-PIN

There is a FORCE_BIAS bit if it is 0b1 it lowers and prioritizes the switchover threshold for the BIAS pin. Intention is to support an external supply of nominal 5V for the VCC2 but still be able to start-up with the VIN supply if the sequencing if the external supply does not meet the start-up timing. The selection of the VCC2 supply follows this behavior:

  • If the BIAS voltages is below the VT+(Force,BIAS) , then the VIN gets selected.
  • If the BIAS voltage is above VT+(Force,BIAS) , then the BIAS gets selected regardless of VIN being above the VT+(VCC,SUP)