JAJSRI9A October   2023  – March 2024 LM51772

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 概要 (続き)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Buck-Boost Control Scheme
        1. 8.3.1.1 Buck Mode
        2. 8.3.1.2 Boost Mode
        3. 8.3.1.3 Buck-Boost Mode
      2. 8.3.2  Power Save Mode
      3. 8.3.3  Programmable Conduction Mode PCM
      4. 8.3.4  Reference System
        1. 8.3.4.1 VIO LDO and nRST-PIN
      5. 8.3.5  Supply Voltage Selection – VMAX Switch and Selection Logic
      6. 8.3.6  Enable and Undervoltage Lockout
        1. 8.3.6.1 UVLO
        2. 8.3.6.2 VDET Comparator
      7. 8.3.7  Internal VCC Regulator
        1. 8.3.7.1 VCC1 Regulator
        2. 8.3.7.2 VCC2 Regulator
      8. 8.3.8  Error Amplifier and Control
        1. 8.3.8.1 Output Voltage Regulation
        2. 8.3.8.2 Internal Output Voltage Regulation
        3. 8.3.8.3 Dynamic Voltage Scaling
      9. 8.3.9  Short Circuit - Hiccup Protection
      10. 8.3.10 Current Monitor/Limiter
        1. 8.3.10.1 Overview
        2. 8.3.10.2 Output Current Limitation
        3. 8.3.10.3 Output Current Monitor
      11. 8.3.11 Oscillator Frequency Selection
      12. 8.3.12 Frequency Synchronization
      13. 8.3.13 Output Voltage Tracking
        1. 8.3.13.1 Analog Voltage Tracking
        2. 8.3.13.2 Digital Voltage Tracking
      14. 8.3.14 Slope Compensation
      15. 8.3.15 Configurable Soft Start
      16. 8.3.16 Drive Pin
      17. 8.3.17 Dual Random Spread Spectrum – DRSS
      18. 8.3.18 Gate Driver
      19. 8.3.19 Cable Drop Compensation (CDC)
      20. 8.3.20 CFG-pin and R2D Interface
      21. 8.3.21 Advanced Monitoring Features
        1. 8.3.21.1  Overview
        2. 8.3.21.2  BUSY
        3. 8.3.21.3  OFF
        4. 8.3.21.4  VOUT
        5. 8.3.21.5  IOUT
        6. 8.3.21.6  INPUT
        7. 8.3.21.7  TEMPERATURE
        8. 8.3.21.8  CML
        9. 8.3.21.9  OTHER
        10. 8.3.21.10 ILIM_OP
        11. 8.3.21.11 nFLT/nINT Pin Output
        12. 8.3.21.12 Status Byte
      22. 8.3.22 Protection Features
        1. 8.3.22.1  Thermal Shutdown (TSD)
        2. 8.3.22.2  Over Current Protection
        3. 8.3.22.3  Output Over Voltage Protection 1 (OVP1)
        4. 8.3.22.4  Output Over Voltage Protection 2 (OVP2)
        5. 8.3.22.5  Input Voltage Protection (IVP)
        6. 8.3.22.6  Input Voltage Regulation (IVR)
        7. 8.3.22.7  Power Good
        8. 8.3.22.8  Boot-Strap Under Voltage Protection
        9. 8.3.22.9  Boot-strap Over Voltage Clamp
        10. 8.3.22.10 CRC - CHECK
    4. 8.4 Device Functional Modes
      1. 8.4.1 Overview
      2. 8.4.2 Logic State Description
    5. 8.5 Programming
      1. 8.5.1 I2C Bus Operation
      2. 8.5.2 Clock Stretching
      3. 8.5.3 Data Transfer Formats
      4. 8.5.4 Single READ from a Defined Register Address
      5. 8.5.5 Sequential READ Starting from a Defined Register Address
      6. 8.5.6 Single WRITE to a Defined Register Address
      7. 8.5.7 Sequential WRITE Starting at a Defined Register Address
  10. 9 LM51772 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Custom Design with WEBENCH Tools
        2. 10.2.2.2  Frequency
        3. 10.2.2.3  Feedback Divider
        4. 10.2.2.4  Inductor and Current Sense Resistor Selection
        5. 10.2.2.5  Output Capacitor
        6. 10.2.2.6  Input Capacitor
        7. 10.2.2.7  Slope Compensation
        8. 10.2.2.8  UVLO Divider
        9. 10.2.2.9  Soft-Start Capacitor
        10. 10.2.2.10 MOSFETs QH1 and QL1
        11. 10.2.2.11 MOSFETs QH2 and QL2
        12. 10.2.2.12 Loop Compensation
        13. 10.2.2.13 External Component Selection
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 Power Stage Layout
        2. 10.4.1.2 Gate Driver Layout
        3. 10.4.1.3 Controller Layout
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.2.2.1 Custom Design with WEBENCH Tools

Click here to create a custom design using the LM51772 device with the WEBENCH® Power Designer.

  1. Start by entering your VIN, VOUT and IOUT requirements.
  2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and compare this design with other possible solutions from Texas Instruments.
  3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real time pricing and component availability.
  4. In most cases, you will also be able to:
    • Run electrical simulations to see important waveforms and circuit performance,
    • Run thermal simulations to understand the thermal performance of your board,
    • Export your customized schematic and layout into popular CAD formats,
    • Print PDF reports for the design, and share your design with colleagues.
  5. Get more information about WEBENCH tools at www.ti.com/webench.