JAJSRI9A October   2023  – March 2024 LM51772

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 概要 (続き)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Buck-Boost Control Scheme
        1. 8.3.1.1 Buck Mode
        2. 8.3.1.2 Boost Mode
        3. 8.3.1.3 Buck-Boost Mode
      2. 8.3.2  Power Save Mode
      3. 8.3.3  Programmable Conduction Mode PCM
      4. 8.3.4  Reference System
        1. 8.3.4.1 VIO LDO and nRST-PIN
      5. 8.3.5  Supply Voltage Selection – VMAX Switch and Selection Logic
      6. 8.3.6  Enable and Undervoltage Lockout
        1. 8.3.6.1 UVLO
        2. 8.3.6.2 VDET Comparator
      7. 8.3.7  Internal VCC Regulator
        1. 8.3.7.1 VCC1 Regulator
        2. 8.3.7.2 VCC2 Regulator
      8. 8.3.8  Error Amplifier and Control
        1. 8.3.8.1 Output Voltage Regulation
        2. 8.3.8.2 Internal Output Voltage Regulation
        3. 8.3.8.3 Dynamic Voltage Scaling
      9. 8.3.9  Short Circuit - Hiccup Protection
      10. 8.3.10 Current Monitor/Limiter
        1. 8.3.10.1 Overview
        2. 8.3.10.2 Output Current Limitation
        3. 8.3.10.3 Output Current Monitor
      11. 8.3.11 Oscillator Frequency Selection
      12. 8.3.12 Frequency Synchronization
      13. 8.3.13 Output Voltage Tracking
        1. 8.3.13.1 Analog Voltage Tracking
        2. 8.3.13.2 Digital Voltage Tracking
      14. 8.3.14 Slope Compensation
      15. 8.3.15 Configurable Soft Start
      16. 8.3.16 Drive Pin
      17. 8.3.17 Dual Random Spread Spectrum – DRSS
      18. 8.3.18 Gate Driver
      19. 8.3.19 Cable Drop Compensation (CDC)
      20. 8.3.20 CFG-pin and R2D Interface
      21. 8.3.21 Advanced Monitoring Features
        1. 8.3.21.1  Overview
        2. 8.3.21.2  BUSY
        3. 8.3.21.3  OFF
        4. 8.3.21.4  VOUT
        5. 8.3.21.5  IOUT
        6. 8.3.21.6  INPUT
        7. 8.3.21.7  TEMPERATURE
        8. 8.3.21.8  CML
        9. 8.3.21.9  OTHER
        10. 8.3.21.10 ILIM_OP
        11. 8.3.21.11 nFLT/nINT Pin Output
        12. 8.3.21.12 Status Byte
      22. 8.3.22 Protection Features
        1. 8.3.22.1  Thermal Shutdown (TSD)
        2. 8.3.22.2  Over Current Protection
        3. 8.3.22.3  Output Over Voltage Protection 1 (OVP1)
        4. 8.3.22.4  Output Over Voltage Protection 2 (OVP2)
        5. 8.3.22.5  Input Voltage Protection (IVP)
        6. 8.3.22.6  Input Voltage Regulation (IVR)
        7. 8.3.22.7  Power Good
        8. 8.3.22.8  Boot-Strap Under Voltage Protection
        9. 8.3.22.9  Boot-strap Over Voltage Clamp
        10. 8.3.22.10 CRC - CHECK
    4. 8.4 Device Functional Modes
      1. 8.4.1 Overview
      2. 8.4.2 Logic State Description
    5. 8.5 Programming
      1. 8.5.1 I2C Bus Operation
      2. 8.5.2 Clock Stretching
      3. 8.5.3 Data Transfer Formats
      4. 8.5.4 Single READ from a Defined Register Address
      5. 8.5.5 Sequential READ Starting from a Defined Register Address
      6. 8.5.6 Single WRITE to a Defined Register Address
      7. 8.5.7 Sequential WRITE Starting at a Defined Register Address
  10. 9 LM51772 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Custom Design with WEBENCH Tools
        2. 10.2.2.2  Frequency
        3. 10.2.2.3  Feedback Divider
        4. 10.2.2.4  Inductor and Current Sense Resistor Selection
        5. 10.2.2.5  Output Capacitor
        6. 10.2.2.6  Input Capacitor
        7. 10.2.2.7  Slope Compensation
        8. 10.2.2.8  UVLO Divider
        9. 10.2.2.9  Soft-Start Capacitor
        10. 10.2.2.10 MOSFETs QH1 and QL1
        11. 10.2.2.11 MOSFETs QH2 and QL2
        12. 10.2.2.12 Loop Compensation
        13. 10.2.2.13 External Component Selection
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 Power Stage Layout
        2. 10.4.1.2 Gate Driver Layout
        3. 10.4.1.3 Controller Layout
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Typical values correspond to TJ=25°C. Minimum and maximum limits apply over TJ=-40°C to 125°C. Unless otherwise stated, V(BIAS) =12V
PARAMETER MIN TYP MAX UNIT
SUPPLY CURRENT
Shutdown current into VIN V(VIN) = 48V,  V(BIAS) = 0V V(EN) = 0V TJ = 25°C 3.6 µA
Shutdown current into BIAS  V(VIN) = 0V,  V(EN) = 0V TJ = 25°C 2.8 µA
Quiescent current into BIAS  V(EN) = 3.3V, V(FB) > 1V, uSleep enabled, ILIMCOMP = V(VCC2) , EN_VCC1 = 0b0  TJ = 25°C 25 µA
VCC1 REGULATOR
VCC1 regulation VI = 12.0V ,I(VCC1) = 1mA 5 V
VCC1 drop-out voltage  I(VCC1) = 34mA; VI = 5V 0.6 V
VI = 4.5V 0.6 V
VCC1 sourcing current limit VCC1=GND VI = 12V 34 mA
VCC2 REGULATOR
VCC2 regulation VBIAS 12.0V ,I(VCC2) = 20mA 5 V
VCC2 drop-out voltage  I(VCC2) = 45mA  VI = 4V 130 mV
VI = 3.5V 190 mV
VCC2 sourcing current limit V(VCC2)  ≥ 3V VI = 6V, VBIAS = 12V 260 mA
VT+(VCC2) Positive going treshold  V(VCC2) rising 3.35 V
VT-(VCC2) Negative going treshold  V(VCC2) falling 3.05 V
VT+(Force,BIAS) Positive going treshold for Forced V(BIAS) FORCE_BIASPIN = 0b1 4.4 V
VT+(VCC2,SUP) Positive going treshold for LDO switch-over  6.5 V
VCC2 UVLO  rising detection delay time  V(VCC2) rising 100 µs
nRST
VT+(nRST) Enable positive-going threshold  nRSTrising 1.4 V
VT-(nRST) Enable negative-going threshold  nRST falling 0.35 V
EN/UVLO
VT+(UVLO) UVLO positive-going threshold  V(EN/UVLO) rising 1.25 V
VT-(UVLO) UVLO negative-going threshold  V(EN/UVLO) falling 1.2 V
Vhyst(UVLO) UVLO threshold hysteresis V(EN/UVLO) falling 50 mV
IUVLO UVLO hystereses sinking current V(EN/UVLO) < 1.26V 5 µA
td(UVLO) UVLO  detection delay time  V(EN/UVLO) falling; 30 µs
SYNC
VT+(SYNC) Sync input positive going threshold 1.19 V
VT-(SYNC) Sync input negative going threshold 0.41 V
Sync activity detection frequency 99 kHz
td(Det,Sync) Sync activity detection frequency threshold refered to f(SYNC)  3 cycles
SYNC output drive streght  EN_SYNC_OUT = 0b1
V(VCC2) = 5V 		 sink –38 mA
source  52 mA
SOFT-START
I(SS) Soft-start current 10 uA

SS pull-down switch RDS(on)
 		 V(SS) = 1V 21 Ω
td(DISCH;SS) SS Pin discharge time  Time from internal SS dischrage until the soft-start current can charge the pin again 500 µs
td(EN_SS) SS Pin charg delay time Internal delay until soft-start current starts 4 µs
V(SS,clamp) Clamp Voltage for SS pin 4.1 V
VOUT TRACKING
VT+(DTRK) DTRK positive-going threshold  V(DTRK) rising 1.19 V
VT-(DTRK) DTRK negative-going threshold  V(DTRK) falling 0.41 V
DTRK activity dectection frequency DTRK activity detection frequency 148 kHz
td(DTRK) DTRK detection delay time  3 cycles
fc(LPF) Corner freqeuncy of internal low pass 40 kHz
V(REF)voltage offset error  V(REF)voltage offset error  f(DTRK) = 500kHz, duty = 50% ±10 mV
PULSE WIDTH MODULATION
Switching frequency RRT = 14kΩ, trimmed OSC 2200 kHz
Switching frequency RRT = 15.4kΩ, trimmed OSC 2000 kHz
Switching frequency RRT = 316kΩ, trimmed OSC 100 kHz
Minimum controllable on-time fPWM, RRT = 14kΩ, positive inductor current Boost Mode 59 ns
Buck Mode  105 ns
Minimum controllable off-time Boost Mode 108 ns
Buck Mode  108 ns
RT regulation voltage 0.75 V
MODE SELECTION
VT+(MODE) Mode input positive going threshold 1.19 V
VT-(MODE) Mode input negative going threshold 0.41 V
CURRENT SENSE
Positive peak current  limit threshold  50 mV
Negative peak current limit threshold  –50 mV
OUTPUT CURRENT LIMIT
Current sense amplifier transconductance I2C interface disabled or DISABLE_ILIM_DAC = 0b1; V(ISNSP) > 3.3V; EN_NEG_CL_LIMIT = 0 25 mV ≤ ΔV(ISNS) ≤ 50mV 1 mS
Current sense amplifier output current  I2C interface disabled or DISABLE_ILIM_DAC = 0b1; V(ISNSP) > 3.V; EN_NEG_CL_LIMIT = 0 5 mV 5 µA
25 mV 25 µA
50 mV 50 µA
Offset voltage VISNS > 4.8V TJ= 25℃ 0 mV
VISNS > 4.8V TJ=-40°C to 150°C 0 mV
Current sense amplifier transconductance I2C interface enabled and  DISABLE_ILIM_DAC = 0b0
VISNS > 4.8V;
N_NEG_CL_LIMIT = 0		 ΔV(ISNS) = 30mV and 50mV 500 µS
Current limit  R(ISNS) = 10mΩ±1%; ILIM_THRESHOLD = 0x64 5 A
ΔV(ISNSx) Current limit threshold voltage ILIM_THRESHOLD = 0x14 EN_NEG_CL_LIMIT = 0J=-40°C to 105°C; ISNSP/N ≥ 5V;  10 mV
Current limit threshold voltage ILIM_THRESHOLD = 0x3C 30 mV
Current limit threshold voltage ILIM_THRESHOLD = 0x64 50 mV
Current limit threshold voltage step size from 5mV to 68.5mV 0.5 mV
Postive going threshold to disable ILIM Referred to VCC2 64 %
ISET regulation threshold voltage 1 V
ERROR AMPLIFIER
VREF FB reference Voltage FB reference 1 V
FB pin leakage current  V(FB) = 1V 60 nA
Transconductance 600 µS
COMP sourcing current 150 uA
COMP sinking current 150 uA
COMP clamp voltage V(FB) = 990mV 1.25 V
COMP clamp voltage V(FB) = 1.01V 0.240 V
VT+(SEL,iFB) postive going threshold to select internal FB operation V(FB) rising 2.5 V
OVP
VT+(OVP) Over-voltage rising threshold FB rising referece to VREF 110 %
VT-(OVP) Over-voltage falling threshold FB falling  referece to VREF 105 %
VT+(OVP2) Over-voltage rising threshold V(VOUT) rising  V_OVP2 = 0b111111 55 V
Over-voltage de-glitch time  10 µs
nFLT
nFLT pull-down switch RDSON 1mA sinking 85 Ω
Under-voltage positive going threshold FB rising (referece to VREF) 95 %
Under-voltage negative going threshold FB falling (referece to VREF) 90 %
nFLT off-state leakage V(nFLT)=12V 100 nA
Deglitch filter 20 us
MOSFET DRIVER
tr  Rise time  HG1, HG2, LG1, LG2 CG = 3.3nF 20 ns
tf Fall time  HG1, HG2, LG1, LG2 CG = 3.3nF 15 ns
Gater driver high side on-resistance  LO1, LO2 I(test) = 500mA 1.12 Ω
Gater driver high side on-resistance  HO1, HO2 I(test) = 500mA 1.16 Ω
Gater driver low side on-resistance  LO1, LO2 I(test) = 500mA 0.5 Ω
Gater driver low side on-resistance  HO1, HO2 I(test) = 500mA 0.51 Ω
THERMAL SHUTDOWN
TT+J   Thermal shutdown threshold   Thermal shutdown threshold TJ rising 164 °C
Thermal shutdown hysteresis Thermal shutdown hysteresis 15 °C
THERMAL WARNING
  Thermal warning threshold TJ rising THW_THRESHOLD=0b10 110 °C
Thermal warning typ. programming range 95 140 °C
R2D INTERFACE
Internal reference resistor 31.77 33 34.23 kΩ
RCFG External selection resistor resistance R2D setting #0 0 0.1 kΩ
R2D setting #1 0.49567 0.511 0.52633 kΩ
R2D setting #2 1.1155 1.15 1.1845 kΩ
R2D setting #3 1.8139 1.87 1.9261 kΩ
R2D setting #4 2.6578 2.74 2.8222 kΩ
R2D setting #5 3.7151 3.83 3.9449 kΩ
R2D setting #6 4.9567 5.11 5.2633 kΩ
R2D setting #7 6.2953 6.49 6.6847 kΩ
R2D setting #8 8.0025 8.25 8.4975 kΩ
R2D setting #9 10.185 10.5 10.815 kΩ
R2D setting #10 12.901 13.3 13.699 kΩ
R2D setting #11 15.714 16.2 16.686 kΩ
R2D setting #12 19.885 20.5 21.115 kΩ
R2D setting #13 24.153 24.9 25.647 kΩ
R2D setting #14 29.197 30.1 31.003 kΩ
R2D setting #15 35.405 36.5 37.595 kΩ
Protection/Monitoring
SCP Hiccup mode on time 1 ms
SCP Hiccup mode off time  24 ms
CABLE DROP COMPENSATION
VOUT increase for cable droop compensation with external feedback  R(FB,top) = 100kΩ; CDC_GAIN=0b01 V(CDC) = 0.2V 0.1 V
V(CDC) = 1V 0.5 V
VOUT increase for cable droop compensation with internal feedback  CDC_GAIN=0b01 V(CDC) = 0.2V 0.1 V
V(CDC) = 1V 0.5 V
gm(CDC) CDC current sense amplifier transconductance ΔV(IMON) = 50mV and 30mV V(ISNSP) > 3.3V; EN_NEG_CL_LIMIT = 0 500 uS
CDC current sense amplifier bandwith 1 MHz
Output current CDC ΔV(IMON) = 50mV;
EN_NEG_CL_LIMIT = 0		 25.0 µA
ΔV(IMON) =  25mV;
EN_NEG_CL_LIMIT = 0		 12.5 µA
ΔV(IMON) = 5mV;
EN_NEG_CL_LIMIT = 0		 2.5 µA
ΔV(IMON) = –5mV;
EN_NEG_CL_LIMIT = 0		 –2.5 µA
ΔV(IMON) = –25mV;
EN_NEG_CL_LIMIT = 0		 –12.5 µA
ΔV(IMON) = –50 mV;
EN_NEG_CL_LIMIT = 0		 –25.0 µA
DRIVE PIN
Pull down resistance  SEL_DRV_SUP = 0b00 1400 Ω
Pull up resistance  SEL_DRV_SUP = 0b01 or SEL_DRV_SUP = 0b10,   1500 Ω
Maximum output current  SEL_DRV_SUP = 0b00 sink 9 mA
Maximum output current  SEL_DRV_SUP = 0b01 or SEL_DRV_SUP = 0b10,   source 9 mA
Pull down resistance  SEL_DRV_SUP = 0b11   900 Ω
Pull up resistance  1200
Ω
Maximum output current  sink 9 mA
Maximum output current  source 8 mA
Charge pump switching frequency  100 kHz
OUTPUT DISCHARGE
Output discharge current  VO_DISCH = 0b00 25 mA
VO_DISCH = 0b01  50 mA
VO_DISCH = 0b10 75 mA
Discharge done threshold  0.5 V
SPREAD SPECTRUM
Switching frequency modulation range upper limit 7.8 %
Switching frequency modulation range lower limit –7.8 %