JAJSHQ1A October 2017 – July 2019 LMK04228
PRODUCTION DATA.
Both PLL1 and PLL2 support digital lock detect. Digital lock detect compares the phase between the reference path (R) and the feedback path (N) of the PLL. When the time error (and therefore the phase error) between the two signals is less than a window size (ε) specified by PLL1_WND_SIZE and PLL2_WND_SIZE, a lock detect count increments. When the lock detect count reaches a user specified value, PLL1_DLD_CNT or PLL2_DLD_CNT, lock detect is asserted true. Once digital lock detect is true, a single phase comparison outside the specified window will cause digital lock detect to be asserted false. This is illustrated in Figure 8.
This incremental lock detect count feature functions as a digital filter to ensure that lock detect isn't asserted for only a brief time when the phases of R and N are within the specified tolerance for only a brief time during initial phase lock.
See Digital Lock Detect Frequency Accuracy for more detailed information on programming the registers to achieve a specified frequency accuracy in ppm with lock detect.
The digital lock detect signal can be monitored on the Status_LD1 or Status_LD2 pin. The pin may be programmed to output the status of lock detect for PLL1, PLL2, or both PLL1 and PLL2.
NOTE
In cases where the period of the phase detector frequency approaches the value of the default PLL1_WND_SIZE increment (40 ns), the lock detect circuit will not function with the default value of PLL1_WND_SIZE. For phase detector frequencies at or above 25 MHz, TI recommends setting PLL1_WND_SIZE to 0x02 (19 ns) or a smaller value.