JAJSIB3D August 2017 – February 2021 THS4561
Figure 10-8 and Figure 10-9 show the gain response and the noise results of the circuit shown in Figure 10-7. Figure 10-7 shows a place for a differential input capacitor (shown as 100 fF) but is not used for the simulation results shown in this section. Results in Figure 10-8 illustrate a flat Butterworth filter response at the output nodes going to the ADC. Obtaining the SNR to the ADC input pins, and assuming an 8-VPP full scale (2.83 VRMS), gives the result of Figure 10-9. The 116-dB SNR and 13-µVRMS total noise shown in Figure 10-9 does not limit the performance for any SAR application.