JAJSGA8F september   2018  – february 2023 TPS1663

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Hot Plug-In and In-Rush Current Control
        1. 9.3.1.1 Thermal Regulation Loop
      2. 9.3.2  Undervoltage Lockout (UVLO)
      3. 9.3.3  Overvoltage Protection (OVP)
      4. 9.3.4  Overload and Short Circuit Protection
        1. 9.3.4.1 Overload Protection
        2. 9.3.4.2 Short Circuit Protection
          1. 9.3.4.2.1 Start-Up With Short-Circuit On Output
      5. 9.3.5  Output Power Limiting, PLIM (TPS16632 Only)
      6. 9.3.6  Current Monitoring Output (IMON)
      7. 9.3.7  FAULT Response (FLT)
      8. 9.3.8  Power Good Output (PGOOD)
      9. 9.3.9  IN, P_IN, OUT and GND Pins
      10. 9.3.10 Thermal Shutdown
      11. 9.3.11 Low Current Shutdown Control (SHDN)
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Programming the Current-Limit Threshold R(ILIM) Selection
        2. 10.2.2.2 Undervoltage Lockout and Overvoltage Set Point
        3. 10.2.2.3 Setting Output Voltage Ramp Time (tdVdT)
          1. 10.2.2.3.1 Support Component Selections RPGOOD and C(IN)
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Simple 24-V Power Supply Path Protection
    4. 10.4 Power Supply Recommendations
      1. 10.4.1 Transient Protection
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGE|24
  • PWP|20
サーマルパッド・メカニカル・データ

6 Pin Configuration and Functions

GUID-84F0C4C3-6E78-4638-878A-9FCBEEAA36E7-low.gifFigure 6-1 TPS16630 RGE Package,24-Pin VQFN(Top View)
GUID-158B98CA-EDAA-4023-8CC4-D7CED2951534-low.gifFigure 6-3 TPS16632 RGE Package,24-Pin VQFN(Top View)
GUID-B246D8E9-3444-4DFB-B8BA-761B567722ED-low.gifFigure 6-2 TPS16630 PWP Package,20-Pin HTSSOP(Top View)
Table 6-1 Pin Functions
PIN TYPE#GUID-0035D528-587A-47C9-A095-95416BFE3A8A DESCRIPTION
NAME TPS16630 TPS16632
VQFN HTSSOP VQFN
IN 1 1 1 P Power input. Connects to the DRAIN of the internal FET.
2 2 2
— 3 —
P_IN 5 6 5 P Supply voltage of the device. Always connect P_IN to IN directly.
UVLO 6 7 6 I Input for setting the programmable undervoltage lockout threshold. An undervoltage event turns off the internal FET and asserts FLT to indicate the power-failure.
OVP 7 8 — I Input for setting the adjustable overvoltage protection threshold (for TPS16630 only). An overvoltage event turns off the internal FET and asserts FLT to indicate the overvoltage fault.
PLIM — — 7 I Input for setting the adjustable output power limiting threshold (TPS16632 Only). Connect a resistor across PLIM to GND to set the output power limit. Connect PLIM to GND if PLIM feature is not used. See Output Power Limiting, PLIM (TPS16632 Only) section.
GND 8 9 8 — Connect GND to system ground.
dVdT 9 10 9 I/O A capacitor from this pin to GND sets output voltage slew rate. Leaving this pin floating enables device power up in thermal regulation resulting in fast output charge. See the Hot Pug-In and In-Rush Current Control section.
ILIM 10 11 10 I/O A resistor from this pin to GND sets the overload limit. See Overload and Short Circuit Protection section.
MODE 11 12 11 I Mode selection pin for Overload fault response. See the Device Functional Modes section.
SHDN 12 13 12 I Shutdown pin. Pulling SHDN low makes the device to enter into low power shutdown mode. Cycling SHDN pin voltage resets the device that has latched off due to a fault condition.
IMON 13 14 13 O Analog current monitor output. This pin sources a scaled down ratio of current through the internal FET. A resistor from this pin to GND converts current to proportional voltage. If unused, leave it floating.
FLT 14 15 14 O Fault event indicator. This pin is an open drain output. If unused, leave floating or connect to GND.
PGOOD 16 16 16 O Active High. A high indicates that the internal FET is enhanced. PGOOD goes low when the internal FET is turned OFF during a fault or when SHDN is pulled low. If PGOOD is unused, then connect to GND or leave it floating.
OUT 17 18 17 P Power output of the device.
18 19 18
— 20 —
N.C 3 4 3 — No connect.
4 5 4
15 17 15
19 — 19
20 — 20
21 — 21
22 — 22
23 — 23
24 — 24
PowerPAD™ — Connect PowerPAD to GND plane for heat sinking. Do not use PowerPAD as the only electrical connection to GND.