JAJSES8B
October 2017 – November 2018
TPS2372
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
概略回路図
4
改訂履歴
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
PG Power Good (Converter Enable) Pin Interface
7.3.2
CLSA and CLSB Classification, AUTCLS
7.3.3
DEN Detection and Enable
7.3.4
Internal Pass MOSFET and Inrush Delay Enable, IRSHDL_EN
7.3.5
TPH, TPL and BT PSE Type Indicators
7.3.6
AMPS_CTL, MPS_DUTY and Automatic MPS
7.3.7
VDD Supply Voltage
7.3.8
VSS
7.3.9
Exposed Thermal PAD
7.4
Device Functional Modes
7.4.1
PoE Overview
7.4.2
Threshold Voltages
7.4.3
PoE Startup Sequence
7.4.4
Detection
7.4.5
Hardware Classification
7.4.6
Autoclass
7.4.7
Inrush and Startup
7.4.8
Maintain Power Signature
7.4.9
Startup and Converter Operation
7.4.10
PD Hotswap Operation
7.4.11
Startup and Power Management, PG and TPH, TPL, BT
7.4.12
Using DEN to Disable PoE
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Requirements
8.2.2.1
Input Bridges and Schottky Diodes
8.2.2.2
Protection, D1
8.2.2.3
Capacitor, C1
8.2.2.4
Detection Resistor, RDEN
8.2.2.5
Classification Resistors, RCLSA and RCLSB
8.2.2.6
Opto-isolators for TPH, TPL and BT
8.2.2.7
Automatic MPS and MPS Duty Cycle, RMPS and RMPS_DUTY
8.2.2.8
Internal Voltage Reference, RREF
8.2.2.9
Autoclass
8.2.2.10
Inrush Delay
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
10.3
EMI Containment
10.4
Thermal Considerations and OTSD
10.5
ESD
11
デバイスおよびドキュメントのサポート
11.1
ドキュメントのサポート
11.1.1
関連リンク
11.1.2
関連資料
11.2
ドキュメントの更新通知を受け取る方法
11.3
コミュニティ・リソース
11.4
商標
11.5
静電気放電に関する注意事項
11.6
Glossary
12
メカニカル、パッケージ、および注文情報
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
RGW|20
サーマルパッド・メカニカル・データ
発注情報
jajses8b_oa
6.6
Typical Characteristics
Figure 1.
Detection Bias Current vs PoE Voltage
Figure 3.
Classification Lower Threshold vs Temperature
Figure 5.
Mark Reset Threshold vs Temperature
Figure 7.
Pass FET Resistance vs Temperature, TPS2372-4
Figure 9.
PoE Inrush Current Limit vs Temperature, TPS2372-4
Figure 11.
Inrush Time Delay vs Temperature
Figure 13.
UVLO Falling Threshold vs Temperature
Figure 2.
I
VDD
Bias Current vs Voltage
Figure 4.
Classification Upper Threshold vs Temperature
Figure 6.
Mark Resistance vs Temperature
Figure 8.
PoE Current Limit vs Temperature, TPS2372-4
Figure 10.
Inrush Termination Threshold vs Temperature, TPS2372-4
Figure 12.
UVLO Rising Threshold vs Temperature