JAJSES8B October   2017  – November 2018 TPS2372

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PG Power Good (Converter Enable) Pin Interface
      2. 7.3.2 CLSA and CLSB Classification, AUTCLS
      3. 7.3.3 DEN Detection and Enable
      4. 7.3.4 Internal Pass MOSFET and Inrush Delay Enable, IRSHDL_EN
      5. 7.3.5 TPH, TPL and BT PSE Type Indicators
      6. 7.3.6 AMPS_CTL, MPS_DUTY and Automatic MPS
      7. 7.3.7 VDD Supply Voltage
      8. 7.3.8 VSS
      9. 7.3.9 Exposed Thermal PAD
    4. 7.4 Device Functional Modes
      1. 7.4.1  PoE Overview
      2. 7.4.2  Threshold Voltages
      3. 7.4.3  PoE Startup Sequence
      4. 7.4.4  Detection
      5. 7.4.5  Hardware Classification
      6. 7.4.6  Autoclass
      7. 7.4.7  Inrush and Startup
      8. 7.4.8  Maintain Power Signature
      9. 7.4.9  Startup and Converter Operation
      10. 7.4.10 PD Hotswap Operation
      11. 7.4.11 Startup and Power Management, PG and TPH, TPL, BT
      12. 7.4.12 Using DEN to Disable PoE
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Requirements
        1. 8.2.2.1  Input Bridges and Schottky Diodes
        2. 8.2.2.2  Protection, D1
        3. 8.2.2.3  Capacitor, C1
        4. 8.2.2.4  Detection Resistor, RDEN
        5. 8.2.2.5  Classification Resistors, RCLSA and RCLSB
        6. 8.2.2.6  Opto-isolators for TPH, TPL and BT
        7. 8.2.2.7  Automatic MPS and MPS Duty Cycle, RMPS and RMPS_DUTY
        8. 8.2.2.8  Internal Voltage Reference, RREF
        9. 8.2.2.9  Autoclass
        10. 8.2.2.10 Inrush Delay
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 EMI Containment
    4. 10.4 Thermal Considerations and OTSD
    5. 10.5 ESD
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連リンク
      2. 11.1.2 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGW|20
サーマルパッド・メカニカル・データ
発注情報

7.4.9 Startup and Converter Operation

The internal PoE UVLO (Undervoltage Lock Out) circuit holds the hotswap switch off before the PSE provides full voltage to the PD. This prevents the downstream converter circuits from loading the PoE input during detection and classification. The converter circuits will discharge CBULK while the PD is unpowered. Thus V(VDD-RTN) will be a small voltage just after full voltage is applied to the PD, as seen in Figure 17. The PSE drives the PI voltage to the operating range once it has decided to power up the PD. When VVDD rises above the UVLO turn-on threshold (VUVLO_R, approximately 38 V) with RTN high, the TPS2372-3 and TPS2372-4 enables the hotswap MOSFET with inrush current limit (~200 mA for TPS2372-3 and ~335 mA for TPS2372-4) as seen in Figure 19. The PG pin is in low state while CBULK charges and VRTN falls from VVDD to nearly VVSS. PG output is maintained low during that time, to avoid additional loading between VVDD and VRTN that could prevent successful PD and subsequent converter start up. Once the inrush current falls about 10% below the inrush current limit, the PD current limit switches to the operational level (approximately 1.85 A for TPS2372-3 and approximately 2.2 A for TPS2372-4).

Additionally, as seen in Figure 19 once the inrush period duration has also exceeded ~81.5 ms, if IRSHDL_EN is open (this delay does not apply if connect to RTN), PG output becomes high impedance, allowing the downstream converter circuitry to start. In typical lighting applications, this allows a low power converter to start powering a microcontroller, which subsequently turns ON a high power LED driver. As seen in Figure 20, the converter soft-start introduces a slight additional delay before the transition to a higher power mode. TPH, TPL and BT outputs are enabled within tTPLHBT following PG going from low to open.

TPS2372 Power_Up_and_Start_72_SLUSCD1.gifFigure 19. Power Up and Start
TPS2372 Startup_Timing_72_SLUSCD1.gifFigure 20. Power Up and Start

If VVDD-VVSS drops below the lower PoE UVLO (VUVLO_F, ~32 V), the hotswap switch is turned off, but the PG output remains high impedance allowing the converter to continue operating until the converter's UVLO threshold is reached.