JAJSES8B October   2017  – November 2018 TPS2372


  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PG Power Good (Converter Enable) Pin Interface
      2. 7.3.2 CLSA and CLSB Classification, AUTCLS
      3. 7.3.3 DEN Detection and Enable
      4. 7.3.4 Internal Pass MOSFET and Inrush Delay Enable, IRSHDL_EN
      5. 7.3.5 TPH, TPL and BT PSE Type Indicators
      6. 7.3.6 AMPS_CTL, MPS_DUTY and Automatic MPS
      7. 7.3.7 VDD Supply Voltage
      8. 7.3.8 VSS
      9. 7.3.9 Exposed Thermal PAD
    4. 7.4 Device Functional Modes
      1. 7.4.1  PoE Overview
      2. 7.4.2  Threshold Voltages
      3. 7.4.3  PoE Startup Sequence
      4. 7.4.4  Detection
      5. 7.4.5  Hardware Classification
      6. 7.4.6  Autoclass
      7. 7.4.7  Inrush and Startup
      8. 7.4.8  Maintain Power Signature
      9. 7.4.9  Startup and Converter Operation
      10. 7.4.10 PD Hotswap Operation
      11. 7.4.11 Startup and Power Management, PG and TPH, TPL, BT
      12. 7.4.12 Using DEN to Disable PoE
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Requirements
        1.  Input Bridges and Schottky Diodes
        2.  Protection, D1
        3.  Capacitor, C1
        4.  Detection Resistor, RDEN
        5.  Classification Resistors, RCLSA and RCLSB
        6.  Opto-isolators for TPH, TPL and BT
        7.  Automatic MPS and MPS Duty Cycle, RMPS and RMPS_DUTY
        8.  Internal Voltage Reference, RREF
        9.  Autoclass
        10. Inrush Delay
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 EMI Containment
    4. 10.4 Thermal Considerations and OTSD
    5. 10.5 ESD
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連リンク
      2. 11.1.2 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報



  • RGW|20

Hardware Classification

Hardware classification allows a PSE to determine a PD’s power requirements before powering, and helps with power management once power is applied. Type 2, 3, and 4 hardware classification permits high power PDs to determine whether the PSE can support its high-power operation. The number of class cycles generated by the PSE prior to turn on indicates to the PD if it allots the power requested or if the allocated power is less than requested, in which case there is power demotion as shown in

Table 3. A Type 2 PD always presents Class 4 in hardware to indicate that it is a 25.5W device. A Class 5 or 6 Type 3 PD presents Class 4 in hardware during the first two class events and it presents Class 0 or 1, respectively, for all subsequent class events. A Class 7 or 8 Type 4 PD presents Class 4 in hardware during the first two class events and it presents Class 2 or 3, respectively, for all subsequent class events. A Type 1 PSE will treat a Class 4 to 8 device like a Class 0 device, allotting 13 W if it chooses to power the PD. A Type 2 PSE will treat a Class 5 to 8 device like a Class 4 device, allotting 25.5W if it chooses to power the PD. A Class 4 PD that receives a 2-event class, a Class 5 or 6 PD that receives a 4-event class, or a Class 7 or 8 PD that receives a 5-event class, understands that the PSE has agreed to allocate the PD requested power. In the case where there is power demotion, the PD may choose to not start, or to start while not drawing more power than initially allocated, and request more power through the DLL after startup. The standard requires a Type 2, 3 or 4 PD to indicate that it is underpowered if this occurs. Startup of a high-power PD at lower power than requested implicitly requires some form of powering down sections of the application circuits.

The maximum power entries in Table 1 determine the class the PD must advertise. The PSE may disconnect a PD if it draws more than its stated class power, which may be the hardware class or a DLL-derived power level. The standard permits the PD to draw limited current peaks that increase the instantaneous power above the Table 1 limit; however, the average power requirement always applies.

The TPS2372 implements one- to five-event classification. RCLSA and RCLSB resistor values define the class of the PD. DLL communication is implemented by the Ethernet communication system in the PD and is not implemented by the TPS2372.

The TPS2372 disables classification above VCU_ON to avoid excessive power dissipation. CLSA/B voltage is turned off during PD thermal limiting or when DEN is active. The CLSA and CLSB outputs are inherently current-limited, but should not be shorted to VSS for long periods of time.

Figure 18 shows how classification works for the TPS2372. Transition from state-to-state occurs when comparator thresholds are crossed (see Figure 15 and Figure 16). These comparators have hysteresis, which adds inherent memory to the machine. Operation begins at idle (unpowered by PSE) and proceeds with increasing voltage from left to right. A 2- to 5-event classification follows the (heavy lined) path towards the bottom, ending up with a latched TPL/TPH decode along the lower branch that is highlighted. Once the valid path to the PSE detection is broken, the input voltage must transition below the mark reset threshold to start anew.

TPS2372 Internal_States_72_SLUSCD1.gifFigure 18. Up to Five-Event Class Internal States