JAJSES8B October 2017 – November 2018 TPS2372
The state of BT, TPH and TPL is used to provide information relative to the PSE Type (1-2 or 3-4) and its allocated power. Table 2 lists the encoding corresponding to various combinations of PSE Type, PD Class and allocated power. Table 3 also corresponds to cases where the PSE allocated power is lower than what the PD is requesting. The allocated power is determined by the number of classification cycles having been received. During startup, the TPH, TPL and BT outputs are enabled typically 24 ms after PG went from low to open, to allow the power supply to reach a stable state first. These 3 outputs will return to a high-impedance state if the part enters thermal shutdown, or if VDD-to-VSS voltage falls below ~32 V. Note that in all these cases, as long as VDD-to-VSS voltage remains above the mark reset threshold, the internal logic state of these 3 signals is remembered such that these outputs will be activated accordingly after the startup has completed. This circuit resets when the VDD-to-VSS voltage drops below the mark reset threshold. The TPH, TPL and BT pins can be left unconnected if not used.
|PSE Type||PD Class||NUMBER OF CLASS CYCLES||PSE ALLOCATED POWER AT PD (W)||TPH||TPL||BT(1)|
|PSE Type||PD Class||NUMBER OF CLASS CYCLES||PSE ALLOCATED POWER AT PD (W)||TPH||TPL||BT|