JAJSES8B October   2017  – November 2018 TPS2372


  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PG Power Good (Converter Enable) Pin Interface
      2. 7.3.2 CLSA and CLSB Classification, AUTCLS
      3. 7.3.3 DEN Detection and Enable
      4. 7.3.4 Internal Pass MOSFET and Inrush Delay Enable, IRSHDL_EN
      5. 7.3.5 TPH, TPL and BT PSE Type Indicators
      6. 7.3.6 AMPS_CTL, MPS_DUTY and Automatic MPS
      7. 7.3.7 VDD Supply Voltage
      8. 7.3.8 VSS
      9. 7.3.9 Exposed Thermal PAD
    4. 7.4 Device Functional Modes
      1. 7.4.1  PoE Overview
      2. 7.4.2  Threshold Voltages
      3. 7.4.3  PoE Startup Sequence
      4. 7.4.4  Detection
      5. 7.4.5  Hardware Classification
      6. 7.4.6  Autoclass
      7. 7.4.7  Inrush and Startup
      8. 7.4.8  Maintain Power Signature
      9. 7.4.9  Startup and Converter Operation
      10. 7.4.10 PD Hotswap Operation
      11. 7.4.11 Startup and Power Management, PG and TPH, TPL, BT
      12. 7.4.12 Using DEN to Disable PoE
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Requirements
        1.  Input Bridges and Schottky Diodes
        2.  Protection, D1
        3.  Capacitor, C1
        4.  Detection Resistor, RDEN
        5.  Classification Resistors, RCLSA and RCLSB
        6.  Opto-isolators for TPH, TPL and BT
        7.  Automatic MPS and MPS Duty Cycle, RMPS and RMPS_DUTY
        8.  Internal Voltage Reference, RREF
        9.  Autoclass
        10. Inrush Delay
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 EMI Containment
    4. 10.4 Thermal Considerations and OTSD
    5. 10.5 ESD
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連リンク
      2. 11.1.2 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報



  • RGW|20

PD Hotswap Operation

IEEE802.3bt includes new PSE output limiting requirements for Type 3 and 4 operation to cover higher power and 4-pair applications. Type 2, 3 and 4 PSEs must meet an output current vs time template with specified minimum and maximum sourcing boundaries. The peak output current per each 2-pair may be as high as 50 A for 10 μs or 1.75 A for 75 ms, and the total peak current becomes twice these values when power is delivered over 4 pairs. This makes robust protection of the PD device even more important than it was in IEEE 802.3-2012.

The internal hotswap MOSFET is protected against output faults and input voltage steps with a current limit and deglitched (time-delay filtered) foldback. An overload on the pass MOSFET engages the current limit, with V(RTN-VSS) rising as a result. If V(RTN-VSS) rises above approximately 14.5 V for longer than approximately 1.65 ms, the current limit reverts to the inrush value and PG output is forced low which turns off the converter, although there is no minimum inrush delay period (81.5-ms) applicable in this case. The 1.65-ms deglitch feature prevents momentary transients from causing a PD reset, provided that recovery lies within the bounds of the hotswap and PSE protection. Figure 21 shows an example of the RTN current profile during VDD to RTN short circuit, using 5-ohm load impedance. The hotswap MOSFET goes into current limit, causing the RTN voltage to increase. Once VRTN exceeds 14.5 V, IRTN, which was clamped to the current limit drops to the level of inrush current limit after 1.65 ms.

The inrush current limit is also reestablished when V(VDD-VSS) drops below UVLO then rises above it.

TPS2372 Response_to_PD_Short_Circuit_72_SLUSCD1.gifFigure 21. Response to PD Output Short Circuit

The PD control has thermal sensors that protect the internal hotswap MOSFET and the MPS pulsed current driver. Conditions like startup or operation into a VDD-to-RTN short cause high power dissipation in the MOSFET. An over-temperature shutdown (OTSD) turns off the hotswap MOSFET, the class regulator, and the MPS driver, which are restarted after the device cools. The hotswap MOSFET will be re-enabled and the TPS2372 will return to inrush phase when exiting from an overtemperature event. Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET to turn off.

The hotswap switch will be forced off under the following conditions:

  1. V(DEN –VSS) < VPD-DIS when V(VDD-VSS) is in the operational range,
  2. PD is over-temperature, or
  3. V(VDD –VSS) < PoE UVLO falling threshold (approximately 32 V).