JAJSES8B October   2017  – November 2018 TPS2372


  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PG Power Good (Converter Enable) Pin Interface
      2. 7.3.2 CLSA and CLSB Classification, AUTCLS
      3. 7.3.3 DEN Detection and Enable
      4. 7.3.4 Internal Pass MOSFET and Inrush Delay Enable, IRSHDL_EN
      5. 7.3.5 TPH, TPL and BT PSE Type Indicators
      6. 7.3.6 AMPS_CTL, MPS_DUTY and Automatic MPS
      7. 7.3.7 VDD Supply Voltage
      8. 7.3.8 VSS
      9. 7.3.9 Exposed Thermal PAD
    4. 7.4 Device Functional Modes
      1. 7.4.1  PoE Overview
      2. 7.4.2  Threshold Voltages
      3. 7.4.3  PoE Startup Sequence
      4. 7.4.4  Detection
      5. 7.4.5  Hardware Classification
      6. 7.4.6  Autoclass
      7. 7.4.7  Inrush and Startup
      8. 7.4.8  Maintain Power Signature
      9. 7.4.9  Startup and Converter Operation
      10. 7.4.10 PD Hotswap Operation
      11. 7.4.11 Startup and Power Management, PG and TPH, TPL, BT
      12. 7.4.12 Using DEN to Disable PoE
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Requirements
        1.  Input Bridges and Schottky Diodes
        2.  Protection, D1
        3.  Capacitor, C1
        4.  Detection Resistor, RDEN
        5.  Classification Resistors, RCLSA and RCLSB
        6.  Opto-isolators for TPH, TPL and BT
        7.  Automatic MPS and MPS Duty Cycle, RMPS and RMPS_DUTY
        8.  Internal Voltage Reference, RREF
        9.  Autoclass
        10. Inrush Delay
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 EMI Containment
    4. 10.4 Thermal Considerations and OTSD
    5. 10.5 ESD
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連リンク
      2. 11.1.2 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報



  • RGW|20

PoE Overview

The following text is intended as an aid in understanding the operation of the TPS2372 but not as a substitute for the IEEE 802.3bt standard. The pending IEEE 802.3bt standard is an update to IEEE 802.3-2012 clause 33 (PoE), adding 4-pair power, high-power options, additional features and enhanced classification. Generally speaking, a device compliant to IEEE 802.3-2012 is referred to as a Type 1 (Class 0-3) or 2 (Class 4) device, and devices with higher power and enhanced classification will be referred to as Type 3 (Class 5,6) or 4 (Class 7,8) devices. Type 3 devices will also include Class 0-4 devices that are 4-pair capable. Standards change and should always be referenced when making design decisions.

The IEEE 802.3bt standard defines a method of safely powering a PD (powered device) over a cable by power sourcing equipment (PSE), and then removing power if a PD is disconnected. The process proceeds through an idle state and three operational states of detection, classification, and operation. There is also a fourth operational state used by Type 3 and 4 PSEs, called "connection check", to determine if the PD has same (single interface) or independent (dual interface or commonly referred to "dual-signature" in the IEEE802.3bt standard) classification signature on each pairset. The PSE leaves the cable unpowered (idle state) while it periodically looks to see if something has been plugged in; this is referred to as detection, and also includes connection check if Type 3 or 4 PSE. The low power levels used during detection and connection check are unlikely to damage devices not designed for PoE. If a valid PD signature is present, the PSE may inquire how much power the PD requires; this is referred to as classification. The PSE may then power the PD if it has adequate capacity.

Type 3 or Type 4 PSEs are required to do an enhanced hardware classification of Type 3 or 4 respectively. Type 2 PSEs are required to do Type 1 hardware classification plus a data-layer classification, or an enhanced Type 2 hardware classification. Type 1 PSEs are not required to do hardware or data link layer (DLL) classification. A Type 3 or Type 4 PD must do respectively Type 3 or Type 4 hardware classification as well as DLL classification. A Type 2 PD must do Type 2 hardware classification as well as DLL classification. The PD may return the default, 13-W current-encoded class, or one of four other choices if Type 2, one of six other choices if Type 3, and one of eight other choices if Type 4. DLL classification occurs after power-on and the Ethernet data link has been established.

The Autoclass function is optional for both the PSE and the PD.

Once started, the PD must present a maintain power signature (MPS) to assure the PSE that it is still present. The PSE monitors its output for a valid MPS, and turns the port off if it loses the MPS. Loss of the MPS returns the PSE to the idle state. Figure 15 shows the operational states as a function of PD input voltage.

TPS2372 Operational_States_SLUSCD1.gifFigure 15. Operational States

The PD input, typically an RJ-45 eight-lead connector, is referred to as the power interface (PI). PD input requirements differ from PSE output requirements to account for voltage drops and operating margin. The standard allots the maximum loss to the cable regardless of the actual installation to simplify implementation. IEEE 802.3-2008 was designed to run over infrastructure including ISO/IEC 11801 class C (CAT3 per TIA/EIA-568) that may have had AWG 26 conductors. IEEE 802.3at Type 2 and IEEE 802.3bt Type 3 cabling power loss allotments and voltage drops have been adjusted for 12.5-Ω power loops per ISO/IEC11801 class D (CAT5 or higher per TIA/EIA-568, typically AWG 24 conductors). Table 6 shows key operational limits broken out for the two revisions of the standard.

Table 6. Comparison of Operational Limits

POWER ≤ 13 W POWER > 13 W
802.3at (Type 1)
20 Ω 15.4 W 44 V 13 W 37 V – 57 V N/A
802.3bt (Type 3) 12.5 Ω 50 V
802.3at (Type 2)
802.3bt (Type 3)
12.5 Ω 30 W 50 V 25.5 W 37 V – 57 V 42.5 V – 57 V
802.3bt (Type 3) 6.25 Ω (4-pair) 60 W 50 V 51 W N/A 42.5 V - 57 V
802.3bt (Type 4) 6.25 Ω (4-pair) 90 W 52 V 71.3 W N/A 41.2 V - 57 V

The PSE can apply voltage either between the RX and TX pairs (pins 1–2 and 3–6 for 10baseT or 100baseT), or between the two spare pairs (4–5 and 7–8). Power application to the same pin combinations in 1000/2.5G/5G/10GbaseT systems is recognized in IEEE 802.3bt. 1000/2.5G/5G/10GbaseT systems can handle data on all pairs, eliminating the spare pair terminology. Type 1 and 2 PSEs are allowed to apply voltage to only one set of pairs at a time, while Type 3 and 4 PSEs may apply power to one or both sets of pairs at a time. The PD uses input diode or active bridges to accept power from any of the possible PSE configurations. The voltage drops associated with the input bridges create a difference between the standard limits at the PI and the TPS2372 specifications.

A compliant Type 2, 3 or 4 PD has power management requirements not present with a Type 1 PD. These requirements include the following:

  1. Must interpret respectively Type 2, 3 or 4 hardware classification.
  2. Must present hardware Class 4 during the first two classfication events, applicable to Type 2 and 4 PDs, as well as to Type 3 PD with Class level 4 or higher.
  3. If Type 3 or 4 single interface PD, it must present hardware Class in the range of 0 to 3 during the third and any subsequent classification events.
  4. Must implement DLL negotiation.
  5. Must behave like a Type 1 PD for 50 ms then must draw less than 400 mA until 80 m after the PSE applies operation voltage (power up), if Type 2 or 3 single interface PD. This covers the PSE inrush period, which is 75 ms maximum.
  6. Should behave like a Type 1 PD for 50 ms then must draw less than 400 mA until 80 ms after the PSE applies operation voltage (power up), if Type 4 single interface PD.
  7. Must not draw more than 60 mA and 5 mA any time the input voltage falls below respectively 30 V and 10 V.
  8. Must not draw more than 13 W if it has not received at least a Type 2 hardware classification or received permission through DLL.
  9. Must not draw more than 25.5 W if it has not received at least 4 classification events or received permission through DLL.
  10. Must not draw more than 51 W if it has not received at least 5 classification events or received permission through DLL.
  11. Must meet various operating and transient templates.
  12. Optionally monitor for the presence or absence of an adapter (assume high power).

As a result of these requirements, the PD must be able to dynamically control its loading, and monitor TPL and TPH for changes. In cases where the design needs to know specifically if an adapter is plugged in and operational, the adapter should be individually monitored, typically with an optocoupler.