JAJSHI3C March 2019 – October 2019 TPS23881
COMMAND = 60h with 1 Data Byte, Read/Write
|LEGEND: R/W = Read/Write; R = Read only; -n = value after reset|
|7||PROG_SEL||R/W||0||I2C Programming select bit.
1 = SRAM I2C read/write is enabled
0 = SRAM I2C read/write is disabled.
|6||CPU_RST||R/W||0||CPU Reset bit
1 = Internal CPU is held in RESET
0 = Internal CPU is active
This is strictly a CPU reset. Toggling this bit reset the cpu only and will not change any contents of the I2C registers
|4||PAR_EN||R/W||0|| SRAM Parity Enable bit:
1 = SRAM Parity Check will be enabled
0 = SRAM Parity Check will be disabled
It is recommended that the Parity function be enable whenever SRAM is being used
|3||RAM_EN||R/W||0||SRAM Enable bit
1 = SRAM will be enabled and the internal CPU will run from both SRAM and internal ROM
0 = Internal CPU will run from internal ROM only
This bit needs to be set to a 1 after SRAM programing to enable the utilization of the SRAM code
|2||PAR_SEL||R/W||0||SRAM Parity Select bit: Setting this bit to a 1 in conjunction with the RZ/W bit enables access to the SRAM Parity bits.
1 = Parity bits read/write is enabled
0 = Parity bits read/write is disabled
|1||R/WZ||R/W||0||SRAM Read/Write select bit:
0 = SRAM Write – SRAM data is written with a write to 0x61h
1 = SRAM Read – SRAM data is read with a read from 0x61h
SRAM data can be continuously read/written over I2C until a STOP bit is sent.
|0||CLR_PTR||R/W||0||Clear Address Pointer bit:
1 = Resets the memory address pointer
0 = Releases pointer for use
In order to ensure proper programming, this bit should be toggled (0-1-0) to writing or reading the SRAM or Parity memory.
Upon power up, it is recommenced that the TPS23881's SRAM be programmed to the latest version of code available for download through the TI mySecure Software webpage.. All I2C traffic other than those commands outlined below to program the SRAM shall be deferred until after the SRAM programming sequences below are complete.
For TPS23881 applications choosing not to load SRAM and run from the internal ROM only, please consult the SRAM Release notes and ROM Advisory documentation available through the TI mySecure Software webpage.
The SRAM programming control must be completed at the lower I2C address (Channels 1-4). Configuring this registers for the upper I2C device address (Channels 5-8) will not program the SRAM
The SRAM programming needs to be delayed at least 50ms from the initial power on (VPWR and VDD above UVLO) of the device to allow for the device to complete its internal hardware initialization process
0x60h setup for SRAM Programming: Prior to programming/writing the SRAM, the following bits sequence needs to be completed in register 0x60h:
|0 → 1||0 → 1||0||0||0||0||1 → 0||0 → 1 → 0|
The same sequence is required to read the SRAM with the exception that the R/WZ bit needs to be set to “1”.
If the device is in “Safe Mode”, the same sequence as above may be used to reprogram the SRAM.
An I2C write to 0x61h following this sequence actively programs the SRAM program memory starting from the address set in registers 0x62h and 63h.
0x60h setup for SRAM Parity Programming: Following the programming of the SRAM program memory, the following bits sequence needs to be completed in register 0x60h in order to configure the device to program the Parity memory:
|0 → 1||0 → 1||0||0||0||0 → 1||1 → 0||0 → 1 → 0|
The same sequence is required to read the Parity with the exception that the R/WZ bit needs to be set to “1".
An I2C write to 0x61h following this sequence actively programs the Parity memory starting from the address set in registers 0x62h and 63h.
0x60h setup to run from SRAM Program Memory: Upon completion of programming, the following bits sequence needs to be completed in register 0x60h in order to enable the device to run properly out of SRAM:
|1 → 0||1 → 0||0||0 → 1||0 → 1||1 → 0||0||0|
Within 1ms of the completion of the above sequence, the device will complete a compatibility check on the SRAM
If the SRAM load is determined to be “Valid”: Register 0x41h will have a value between 0x01h and 0xFEh, and the device will return to normal operation.
If the SRAM load is determined to be “Invalid”:
• 0x41h will be set to 0xFFh
• The RAM_EN bit will be internally cleared
• The device will operating in “safe mode” until another programming attempt is completed