JAJSHI3C March 2019 – October 2019 TPS23881
COMMAND = 15h with 1 Data Byte, R/W
|LEGEND: R/W = Read/Write; R = Read only; -n = value after reset|
|7–4||OSS4-OSS1||R/W||0||Power priority bits:
When the MBitPrty bit in 0x17 =0:
1 = When the OSS signal is asserted, the corresponding channel is powered off.
0 = OSS signal has no impact on the channel.
For 4-pair wired Ports, these bits control the individual Channel response. In order for both channels of a 4-pair wired port to be disabled, both channels need to be set to 1.
|3–0||DCUT4-DCUT1||R/W||0|| 2-Pair PCUT disable for each channel. Used to prevent removal of the associated channel’s power due to a 2-Pair PCUT fault, regardless of the programming status of the Timing Configuration register. Note that there is still monitoring of ILIM faults.
1: Channel’s PCUT is disabled. This means that an PCUT fault alone will not turn off this channel.
0: Channel’s PCUT is enabled. This enables channel turn off if there is PCUT fault.
If the MbitPrty bit = 1 (0x17h): The OSSn bits must be cleared to ensure proper operation. Refer to registers 0x27/28h for more information on the Multi-bit priority shutdown feature.
If DCUT = 1 for a channel, the channel will not be automatically turned off during a PCUT fault condition. However, the PCUT fault flag will still be operational, with a fault timeout equal to tOVLD.
Any change in the state of DCUTn bits will result in the resetting of the TOVLD timer for that channel.
For 4-pair wired Ports:
These bits control the individual Channel response to a 2-Pair PCUT fault.
If the NCTnn bit in 0x2D = 1 and the 2-Pair PCut is enabled, both channel will be turned off if the overload condition exceeds the tOVLD timeout.
The response to a summed 4-pair PCUT fault is configured in register 0x2Dh.
The OSSn bits are used to determine which channels are shut down in response to an external assertion of the OSS fast shutdown signal.
The turn off procedure due to OSS is similar to a channel reset or change to OFF mode, with the exception that OSS does not cancel any ongoing fault cool down timers. the table below includes the bits that will be cleared when a channel is disabled due to OSS:
|Register||Bits to be reset|
|0x04||CLSCn and DETCn|
|0x06||DISFn and PCUTn|
|0x08||STRTn and ILIMn|
|0x0C-0F||Requested Class and Detection|
|0x10||PGn and PEn|
|0x14||CLEn and DETEn|
|0x1C||ACn and CCnn|
|0x1E-21||2P Policing set to 0xFFh|
|0x2A-2B||4P Policing set to 0xFFh|
|0x2D||NLMnn, NCTnn, 4PPCTnn, and DCDTnn|
|0x30-3F||Channel Voltage and Current Measurements|
|0x44 - 47||Detection Resistance Measurements|
|0x4C-4F||Assigned Class and Previous Class|
it may take upwards of 5 ms before all of the registers are cleared following an OSS event.
Only the bits associated with the channel/port ("n") with OSS enabled will be cleared. Those bits associated with channels/ports remaining in operation will not be changed.
In the event a singular channel of a 4-pair dual signature PD is turned off due to OSS or PCUT fault, power may be reapplied to that channel by setting the PWON bit in 0x19h provided the detection and classification are still valid and the Power Allocation settings in 0x29 are sufficient based on the assigned classification of the powered channel.