JAJSHI3C March 2019 – October 2019 TPS23881
COMMAND = 04h with 1 Data Byte, Read only
COMMAND = 05h with 1 Data Byte, Clear on Read
Active high, each bit corresponds to a particular event that occurred.
Each bit xxx1-4 represents an individual channel.
A read at each location (04h or 05h) returns the same register data with the exception that the Clear on Read command clears all bits of the register. These bits are cleared when channel-n is turned off.
If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.
Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.
|LEGEND: R/W = Read/Write; R = Read only; ; CR = Clear on Read, -n = value after reset|
|7–4||CLSC4–CLSC1||R or CR||0||Indicates that at least one classification cycle occurred if the CLCHE bit in General Mask register is low. Conversely, it indicates when a change of class occurred if the CLCHE bit is set.
1 = At least one classification cycle occurred (if CLCHE = 0) or a change of class occurred (CLCHE = 1)
0 = No classification cycle occurred (if CLCHE = 0) or no change of class occurred (CLCHE = 1)
|3–0||DETC4–DETC1||R or CR||0||Indicates that at least one detection cycle occurred if the DECHE bit in General Mask register is low. Conversely, it indicates when a change in detection occurred if the DECHE bit is set.
1 = At least one detection cycle occurred (if DECHE = 0) or a change in detection occurred (DECHE = 1)
0 = No detection cycle occurred (if DECHE = 0) or no change in detection occurred (DECHE = 1)
For 4-Pair operated ports without a pending PWON command, these bits will be set only after the status is ready for both channels. This is done to prevent the possible scenario of dual interrupts as the second channel completes processing after the first.
The DETCn bits will only be set concurrently within 5ms of completing detection and connection check on both channels
For a 4-pair single signature device, the CLSCn bit will only be set for the pair set that classification was completed on even though the requested class will be given for both channels in registers 0x0C-0F.
For a 4-pair dual signature device only doing discovery in Semi-auto mode, the CLSCn bits will be set concurrently within 5ms of classification being completed on both channels. In manual mode, the CLSCn bits will be set individually within 5ms of classification being completed on each channels.
For 4-pair dual signature devices with a pending PWON command or in Auto mode, the DETCn and CLSCn bits will be set independently as each channel completes its portion of discovery during the dual-signature staggered turn on procedure.