JAJSQ98 july   2020 TSB82AF15-EP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 PCIe Differential Transmitter Output Ranges
    6. 6.6 PCIe Differential Receiver Input Ranges
    7. 6.7 PCIe Differential Reference Clock Input Ranges
    8. 6.8 Electrical Characteristics Over Recommended Operating Conditions (3.3-V I/O)
    9. 6.9 Switching Characteristics
  8. 7 Operating Life Deration
  9. 8 Typical Characteristics
  10. 9 Parameter Measurement Information
  11. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Power-Up/Power-Down Sequencing
        1. 10.3.1.1 Power-Up Sequence
        2. 10.3.1.2 Power-Down Sequence
      2. 10.3.2 TSB82AF15-EP Reset Features
      3. 10.3.3 PCI Express (PCIe) Interface
        1. 10.3.3.1 External Reference Clock
        2. 10.3.3.2 Beacon and Wake
        3. 10.3.3.3 Initial Flow Control Credits
        4. 10.3.3.4 PCIe Message Transactions
      4. 10.3.4 PCI Interrupt Conversion to PCIe Messages
      5. 10.3.5 Two-Wire Serial-Bus Interface
        1. 10.3.5.1 Serial-Bus Interface Implementation
        2. 10.3.5.2 Serial-Bus Interface Protocol
        3. 10.3.5.3 Serial-Bus EEPROM Application
        4. 10.3.5.4 Accessing Serial-Bus Devices Through Software
      6. 10.3.6 General-Purpose I/O (GPIO) Interface
    4. 10.4 Device Functional Modes
      1. 10.4.1 Advanced Error Reporting Registers
      2. 10.4.2 Data Error Forwarding Capability
      3. 10.4.3 Set Slot Power Limit Functionality
      4. 10.4.4 PCIe and PCI Bus Power Management
    5. 10.5 Programming
      1. 10.5.1 1394b OHCI Controller Functionality
        1. 10.5.1.1 1394b OHCI Power Management
        2. 10.5.1.2 1394b OHCI and V AUX
        3. 10.5.1.3 1394b OHCI and Reset Options
        4. 10.5.1.4 1394b OHCI PCI Bus Master
        5. 10.5.1.5 1394b OHCI Subsystem Identification
        6. 10.5.1.6 1394b OHCI PME Support
    6. 10.6 Register Maps
      1. 10.6.1 Classic PCI Configuration Space
        1. 10.6.1.1  Vendor ID Register
        2. 10.6.1.2  Device ID Register
        3. 10.6.1.3  Command Register
        4. 10.6.1.4  Status Register
        5. 10.6.1.5  Class Code and Revision ID Register
        6. 10.6.1.6  Cache Line Size Register
        7. 10.6.1.7  Primary Latency Timer Register
        8. 10.6.1.8  Header Type Register
        9. 10.6.1.9  BIST Register
        10. 10.6.1.10 Device Control Base Address Register
        11. 10.6.1.11 Scratchpad RAM Base Address
        12. 10.6.1.12 Primary Bus Number Register
        13. 10.6.1.13 Secondary Bus Number Register
        14. 10.6.1.14 Subordinate Bus Number Register
        15. 10.6.1.15 Secondary Latency Timer Register
        16. 10.6.1.16 I/O Base Register
        17. 10.6.1.17 I/O Limit Register
        18. 10.6.1.18 Secondary Status Register
        19. 10.6.1.19 Memory Base Register
        20. 10.6.1.20 Memory Limit Register
        21. 10.6.1.21 Prefetchable Memory Base Register
        22. 10.6.1.22 Prefetchable Memory Limit Register
        23. 10.6.1.23 Prefetchable Base Upper 32 Bits Register
        24. 10.6.1.24 Prefetchable Limit Upper 32 Bits Register
        25. 10.6.1.25 I/O Base Upper 16 Bits Register
        26. 10.6.1.26 I/O Limit Upper 16 Bits Register
        27. 10.6.1.27 Capabilities Pointer Register
        28. 10.6.1.28 Interrupt Line Register
        29. 10.6.1.29 Interrupt Pin Register
        30. 10.6.1.30 Bridge Control Register
        31. 10.6.1.31 PM Capability ID Register
        32. 10.6.1.32 Next Item Pointer Register
        33. 10.6.1.33 Power Management Capabilities Register
        34. 10.6.1.34 Power Management Control/Status Register
        35. 10.6.1.35 Power Management Bridge Support Extension Register
        36. 10.6.1.36 Power Management Data Register
        37. 10.6.1.37 MSI Capability ID Register
        38. 10.6.1.38 Next Item Pointer Register
        39. 10.6.1.39 MSI Message Control Register
        40. 10.6.1.40 MSI Message Lower Address Register
        41. 10.6.1.41 MSI Message Upper Address Register
        42. 10.6.1.42 MSI Message Data Register
        43. 10.6.1.43 SSID/SSVID Capability ID Register
        44. 10.6.1.44 Next Item Pointer Register
        45. 10.6.1.45 Subsystem Vendor ID Register
        46. 10.6.1.46 Subsystem ID Register
        47. 10.6.1.47 PCI Express Capability ID Register
        48. 10.6.1.48 Next Item Pointer Register
        49. 10.6.1.49 PCI Express Capabilities Register
        50. 10.6.1.50 Device Capabilities Register
        51. 10.6.1.51 Device Control Register
        52. 10.6.1.52 Device Status Register
        53. 10.6.1.53 Link Capabilities Register
        54. 10.6.1.54 Link Control Register
        55. 10.6.1.55 Link Status Register
        56. 10.6.1.56 Serial-Bus Data Register
        57. 10.6.1.57 Serial-Bus Word Address Register
        58. 10.6.1.58 Serial-Bus Slave Address Register
        59. 10.6.1.59 Serial-Bus Control and Status Register
        60. 10.6.1.60 GPIO Control Register
        61. 10.6.1.61 GPIO Data Register
        62. 10.6.1.62 Control and Diagnostic Register 0
        63. 10.6.1.63 Control and Diagnostic Register 1
        64. 10.6.1.64 PHY Control and Diagnostic Register 2
        65. 10.6.1.65 Subsystem Access Register
        66. 10.6.1.66 General Control Register
        67. 10.6.1.67 TI Proprietary Register
        68. 10.6.1.68 TI Proprietary Register
        69. 10.6.1.69 TI Proprietary Register
        70. 10.6.1.70 Arbiter Control Register
        71. 10.6.1.71 Arbiter Request Mask Register
        72. 10.6.1.72 Arbiter Time-Out Status Register
        73. 10.6.1.73 TI Proprietary Register
        74. 10.6.1.74 TI Proprietary Register
        75. 10.6.1.75 TI Proprietary Register
      2. 10.6.2 PCIe Extended Configuration Space
        1. 10.6.2.1  Advanced Error Reporting Capability ID Register
        2. 10.6.2.2  Next Capability Offset/Capability Version Register
        3. 10.6.2.3  Uncorrectable Error Status Register
        4. 10.6.2.4  Uncorrectable Error Mask Register
        5. 10.6.2.5  Uncorrectable Error Severity Register
        6. 10.6.2.6  Correctable Error Status Register
        7. 10.6.2.7  Correctable Error Mask Register
        8. 10.6.2.8  Advanced Error Capabilities and Control Register
        9. 10.6.2.9  Header Log Register
        10. 10.6.2.10 Secondary Uncorrectable Error Status Register
        11. 10.6.2.11 Secondary Uncorrectable Error Mask Register
        12. 10.6.2.12 Secondary Uncorrectable Error Severity
        13. 10.6.2.13 Secondary Error Capabilities and Control Register
        14. 10.6.2.14 Secondary Header Log Register
      3. 10.6.3 Memory-Mapped TI Proprietary Register Space
        1. 10.6.3.1 Device Control Map ID Register
        2. 10.6.3.2 Revision ID Register
        3. 10.6.3.3 GPIO Control Register
        4. 10.6.3.4 GPIO Data Register
        5. 10.6.3.5 Serial-Bus Data Register
        6. 10.6.3.6 Serial-Bus Word Address Register
        7. 10.6.3.7 Serial-Bus Slave Address Register
        8. 10.6.3.8 Serial-Bus Control and Status Register
      4. 10.6.4 1394 OHCI PCI Configuration Space
        1. 10.6.4.1  Vendor ID Register
        2. 10.6.4.2  Device ID Register
        3. 10.6.4.3  Command Register
        4. 10.6.4.4  Status Register
        5. 10.6.4.5  Class Code and Revision ID Registers
        6. 10.6.4.6  Cache Line Size and Latency Timer Registers
        7. 10.6.4.7  Header Type and BIST Registers
        8. 10.6.4.8  OHCI Base Address Register
        9. 10.6.4.9  TI Extension Base Address Register
        10. 10.6.4.10 CIS Base Address Register
        11. 10.6.4.11 CIS Pointer Register
        12. 10.6.4.12 Subsystem Vendor ID and Subsystem ID Registers
        13. 10.6.4.13 Power Management Capabilities Pointer Register
        14. 10.6.4.14 Interrupt Line and Interrupt Pin Registers
        15. 10.6.4.15 Minimum Grant and Minimum Latency Registers
        16. 10.6.4.16 OHCI Control Register
        17. 10.6.4.17 Capability ID and Next Item Pointer Registers
        18. 10.6.4.18 Power Management Capabilities Register
        19. 10.6.4.19 Power Management Control and Status Register
        20. 10.6.4.20 Power Management Extension Registers
        21. 10.6.4.21 PCI Miscellaneous Configuration Register
        22. 10.6.4.22 Link Enhancement Control Register
        23. 10.6.4.23 Subsystem Access Register
      5. 10.6.5 1394 OHCI Memory-Mapped Register Space
        1. 10.6.5.1  OHCI Version Register
        2. 10.6.5.2  GUID ROM Register
        3. 10.6.5.3  Asynchronous Transmit Retries Register
        4. 10.6.5.4  CSR Data Register
        5. 10.6.5.5  CSR Compare Register
        6. 10.6.5.6  CSR Control Register
        7. 10.6.5.7  Configuration ROM Header Register
        8. 10.6.5.8  Bus Identification Register
        9. 10.6.5.9  Bus Options Register
        10. 10.6.5.10 GUID High Register
        11. 10.6.5.11 GUID Low Register
        12. 10.6.5.12 Configuration ROM Mapping Register
        13. 10.6.5.13 Posted Write Address Low Register
        14. 10.6.5.14 Posted Write Address High Register
        15. 10.6.5.15 Vendor ID Register
        16. 10.6.5.16 Host Controller Control Register
        17. 10.6.5.17 Self-ID Buffer Pointer Register
        18. 10.6.5.18 Self-ID Count Register
        19. 10.6.5.19 Isochronous Receive Channel Mask High Register
        20. 10.6.5.20 Isochronous Receive Channel Mask Low Register
        21. 10.6.5.21 Interrupt Event Register
        22. 10.6.5.22 Interrupt Mask Register
        23. 10.6.5.23 Isochronous Transmit Interrupt Event Register
        24. 10.6.5.24 Isochronous Transmit Interrupt Mask Register
        25. 10.6.5.25 Isochronous Receive Interrupt Event Register
        26. 10.6.5.26 Isochronous Receive Interrupt Mask Register
        27. 10.6.5.27 Initial Bandwidth Available Register
        28. 10.6.5.28 Initial Channels Available High Register
        29. 10.6.5.29 Initial Channels Available Low Register
        30. 10.6.5.30 Fairness Control Register
        31. 10.6.5.31 Link Control Register
        32. 10.6.5.32 Node Identification Register
        33. 10.6.5.33 PHY Control Register
        34. 10.6.5.34 Isochronous Cycle Timer Register
        35. 10.6.5.35 Asynchronous Request Filter High Register
        36. 10.6.5.36 Asynchronous Request Filter Low Register
        37. 10.6.5.37 Physical Request Filter High Register
        38. 10.6.5.38 Physical Request Filter Low Register
        39. 10.6.5.39 Physical Upper Bound Register (Optional Register)
        40. 10.6.5.40 Asynchronous Context Control Register
        41. 10.6.5.41 Asynchronous Context Command Pointer Register
        42. 10.6.5.42 Isochronous Transmit Context Control Register
        43. 10.6.5.43 Isochronous Transmit Context Command Pointer Register
        44. 10.6.5.44 Isochronous Receive Context Control Register
        45. 10.6.5.45 Isochronous Receive Context Command Pointer Register
        46. 10.6.5.46 Isochronous Receive Context Match Register
      6. 10.6.6 1394 OHCI Memory-Mapped TI Extension Register Space
        1. 10.6.6.1 Digital Video (DV) and MPEG2 Timestamp Enhancements
        2. 10.6.6.2 Isochronous Receive Digital Video Enhancements
        3. 10.6.6.3 Isochronous Receive Digital Video Enhancement Registers
        4. 10.6.6.4 Link Enhancement Control Registers
        5. 10.6.6.5 Timestamp Offset Registers
  12. 11Application and Implementation
    1. 11.1 Known exceptions to functional specification (errata).
      1. 11.1.1 Errata # 1: UR bit incorrectly set in the uncorrectable error status register when the ANFES bit is set
        1. 11.1.1.1 Detailed Description
        2. 11.1.1.2 Overall Impact
        3. 11.1.1.3 Workaround Proposal
        4. 11.1.1.4 Corrective Action
      2. 11.1.2 Errata #2: File Transfer Fails When L1 is Enabled
        1. 11.1.2.1 Detailed Description
        2. 11.1.2.2 Overall Impact
        3. 11.1.2.3 Workaround Proposal
        4. 11.1.2.4 Corrective Action
    2. 11.2 Application Information
      1. 11.2.1 Typical Application
      2. 11.2.2 Application Curves
      3. 11.2.3 Design Requirements
  13. 12Power Supply Recommendations
  14. 13Layout
    1. 13.1 Layout Guidelines
  15. 14Device and Documentation Support
    1. 14.1 Device Support
      1. 14.1.1 Device Nomenclature
        1. 14.1.1.1 Documents Conventions
    2. 14.2 Documentation Support
      1. 14.2.1 Related Documentation
    3. 14.3 Receiving Notification of Documentation Updates
    4. 14.4 サポート・リソース
    5. 14.5 Trademarks
    6. 14.6 静電気放電に関する注意事項
    7. 14.7 用語集
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 PCIe Differential Receiver Input Ranges

RXP and RXN. At TJ = –40°C to 125°C, unless otherwise noted.
PARAMETER MIN NOM MAX UNIT COMMENTS
UI Unit interval 399.88 400 400.12 ps Each UI is 400 ps 300 ppm. UI does not account for SSC dictated variations(1)
VRX-DIFFp-p Differential input peak-to-peak voltage 0.175 1.200 V VRX-DIFFp-p = 2*|VRXP - VRXN, |(2)
TRX-EYE Minimum receiver eye width 0.4 UI The maximum interconnect media and transmitter jitter that can be tolerated by the receiver is derived as TRX-MAX-JITTER = 1 - TRX-EYE = 0.6 UI(2) (3)
TRX-EYE-MEDIAN-to-MAX-JITTER Maximum time between jitter median and maximum deviation from median 0.3 UI Jitter is defined as the measurement variation of the crossing points (VRX-DIFFp-p = 0 V) in relation to recovered TX UI. A recovered TX UI is calculated over 3500 consecutive UIs of sample data. Jitter is measured using all edges of the 250 consecutive UIs in the center of the 3500 UIs used for calculating the TX UI.(2) (3)
VRX-CM-ACp AC peak common-mode input voltage 150 mV VRX-CM-ACp = RMS(|VRXP + VRXN|/2 - VRX-CM-DC)
VRX-CM-DC = DC(avg) of |VRXP + VRXN|/2(2)
RLRX-DIFF Differential return loss 10 dB Measured over 50 MHz to 1.25 GHz with the P and N lines biased at +300 mV and - 300 mV, respectively(4)
RLRX-CM Common-mode return loss 6 dB Measured over 50 MHz to 1.25 GHz with the P and N lines biased at +300 mV and 300 mV, respectively(4)
ZRX-DIFF-DC DC differential input impedance 80 100 120 Ω RX dc differential mode impedance(4)
ZRX-DC DC input impedance 40 50 60 Ω Required RXP as well as RXN dc impedance (50 Ω 20% tolerance)(2) (5)
ZRX-HIGH-IMP-D Powered down dc input impedance 200 kΩ Required RXP as well as RXN dc impedance when the receiver terminations do not have power(6)
VRX-IDLE-DET-DIFFp-p Electrical idle detect threshold 65 175 mV VRX-IDLE-DET-DIFFp-p = 2*|VRXP - VRXN| measured at the receiver package terminals
TRX-IDLE-DET-DIFF-ENTER-TIME Unexpected electrical idle enter detect threshold integration time 10 ms An unexpected electrical idle
(VRX-DIFFp-p < VRX-IDLE-DET-DIFFp-p) must be recognized no longer than
TRX-IDLE-DET-DIFF-ENTER-TIME to signal an unexpected idle condition.
(1) No test load is necessarily associated with this value.
(2) Specified at the measurement point and measured over any 250 consecutive UIs. A test load must be used as the RX device when taking measurements. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI is used as a reference for the eye diagram.
(3) A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total UI jitter budget collected over any 250 consecutive TX UIs. It must be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UIs must be used as the reference for the eye diagram.
(4) The receiver input impedance results in a differential return loss greater than or equal to 15 dB with the P line biased to 300 mV and the N line biased to 300 mV and a common-mode return loss greater than or equal to 6 dB (no bias required) over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements for is 50Ω to ground for both the P and N line (i.e., as measured by a vector network analyzer with 50Ω probes). The series capacitors CTX is optional for the return loss measurement.
(5) Impedance during all link training status state machine (LTSSM) states. When transitioning from a PCIe reset to the detect state (the initial state of the LTSSM) there is a 5-ms transition time before receiver termination values must be met on the unconfigured lane of a port.
(6) The RX dc common-mode impedance that exists when no power is present or PCIe reset is asserted. This helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the RX ground.