DLPU040B October   2016  – March 2023 DLP650LNIR , DLPC410

 

  1.   DLP Discovery 4100 Development Platform User’s Guide
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Welcome
  4. 2Overview
    1. 2.1 The DLP Discovery 4100 Development Platform
    2. 2.2 DLP Discovery 4100 Development Platform Photo
    3. 2.3 Key Components
      1. 2.3.1  Xilinx Virtex 5 APPSFPGA
      2. 2.3.2  DLPC410 - Digital Controller for DLP Discovery 4100 Chipset
      3. 2.3.3  DLPA200 - DMD Micromirror Driver
      4. 2.3.4  DLPR410 - Configuration PROM for DLPC410 Controller
      5. 2.3.5  APPSFPGA Flash Configuration PROM
      6. 2.3.6  DMD Connectors
      7. 2.3.7  USB Controller
      8. 2.3.8  50-MHz Oscillator
      9. 2.3.9  DDR2 SODIMM Connector
      10. 2.3.10 Connectors
        1. 2.3.10.1 JTAG Header H1
        2. 2.3.10.2 Mictor Connectors
        3. 2.3.10.3 GPIO Connectors
      11. 2.3.11 Battery
      12. 2.3.12 Power Supplies
        1. 2.3.12.1 J14 Power Connector
        2. 2.3.12.2 J14 Power Connector
        3. 2.3.12.3 REG. 0.9 V
        4. 2.3.12.4 REG. 1.0 V
        5. 2.3.12.5 REG. 1.8 V
        6. 2.3.12.6 REG. 2.5 V
        7. 2.3.12.7 REG. 3.3 V
        8. 2.3.12.8 REG. 12 V
  5. 3Hardware Overview and Setup
    1. 3.1 Getting Started
    2. 3.2 User Connectors and I/O
      1. 3.2.1  J12 Input Power Connector
      2. 3.2.2  J18 Input Power Connector
      3. 3.2.3  J1 USB Connector Pinout
      4. 3.2.4  J3 USB GPIO
      5. 3.2.5  J6 GPIO_A Connector
      6. 3.2.6  J8 DLPC410 Mictor Connector
      7. 3.2.7  J9 USB/APPSFPGA Mictor Connector
      8. 3.2.8  J13 DMD Flex 1 Connector
      9. 3.2.9  J14 DMD Flex 2 Connector
      10. 3.2.10 J15 DDR2 SODIMM Connector
      11. 3.2.11 J16, J17 EXP Connectors
      12. 3.2.12 H1 Xilinx FPGA JTAG Header
    3. 3.3 Configuration Jumpers
      1. 3.3.1 J2 – EXP Voltage Select
      2. 3.3.2 J4 – APPSFPGA Revision Select
      3. 3.3.3 J5 – Shared USB Signal Enable/Disable
      4. 3.3.4 J7 – USB EEPROM Programming Header
      5. 3.3.5 J10 – DLPA200 B Output Enable
    4. 3.4 Switches
      1. 3.4.1 SW1 - APPSFPGA Functional Switches
      2. 3.4.2 SW2 - APPSFPGA Reset
      3. 3.4.3 SW3 - DMD Power Float (Park)
      4. 3.4.4 SW4 - Input Power On/Off
    5. 3.5 Power and Status LEDs
      1. 3.5.1 D1 – USB Connection Indicator
      2. 3.5.2 D2 and D16 – APPSFPGA Done
      3. 3.5.3 D3 and D17 – DLPC410 Done
      4. 3.5.4 D9 – DDC_LED0
      5. 3.5.5 D10 – DDC_LED1
      6. 3.5.6 D11 – VLED0
      7. 3.5.7 D12 – VLED1
    6. 3.6 Test Points
  6. 4Software
    1. 4.1 Overview
      1. 4.1.1 Software Overview
        1. 4.1.1.1 DMD Image Control
        2. 4.1.1.2 Image Commands
    2. 4.2 DLP Discovery 4100 Operation
      1. 4.2.1 Quick Start Guide on Operation
      2. 4.2.2 74
    3. 4.3 Graphical User Interface
      1. 4.3.1 Menu Bar
        1. 4.3.1.1 File Menu
        2. 4.3.1.2 View Menu
        3. 4.3.1.3 DMD Menu
        4. 4.3.1.4 Execution Menu
        5. 4.3.1.5 Test Patterns Menu
        6. 4.3.1.6 Help Menu
      2. 4.3.2 Toolbar
        1. 4.3.2.1 File Menu Buttons
        2. 4.3.2.2 Run, Run Once, Loop Break, Step and Stop Controls
        3. 4.3.2.3 Set Start and End Buttons
        4. 4.3.2.4 Help Button
      3. 4.3.3 Script Commands Window
        1. 4.3.3.1 Load Tab
        2. 4.3.3.2 Reset Tab
        3. 4.3.3.3 Clear Tab
        4. 4.3.3.4 Float Tab
        5. 4.3.3.5 Control Tab
      4. 4.3.4 Status Window
      5. 4.3.5 Script Window
        1. 4.3.5.1 Inserting Commands
        2. 4.3.5.2 Moving Commands
        3. 4.3.5.3 Deleting Commands
    4. 4.4 Script and Status Operations
      1. 4.4.1 Saving Scripts and Statuses
        1. 4.4.1.1 Saving a Script
        2. 4.4.1.2 Saving a Status
      2. 4.4.2 Printing Scripts and Statuses
        1. 4.4.2.1 Printing a Script
        2. 4.4.2.2 Printing a Status
      3. 4.4.3 Opening Scripts and Statuses
      4. 4.4.4 Creating New Scripts and Statuses
        1. 4.4.4.1 Creating a New Script
        2. 4.4.4.2 Creating a New Status
    5. 4.5 DLPC410 Control Window
    6. 4.6 Test Patterns Window
    7. 4.7 About Box
    8. 4.8 Links
  7. 5Related Documentation
  8. 6Appendix
    1. 6.1 Abbreviations and Acronyms
    2. 6.2 Notational Conventions
      1. 6.2.1 Information About Cautions and Warnings
  9. 7Revision History

3.2.10 J15 DDR2 SODIMM Connector

Connector J15 provides a DDR2 SODIMM memory socket. No memory module is included. Memory controller design for the APPSFPGA is not included. For a memory controller reference design, visit www.xilinx.com.

Table 3-10 J15 DDR2 SODIMM Connector
Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name
1 VCC_VREF 2 GND 3 GND 4 DDR2_D4
5 DDR2_D0 6 DDR2_D5 7 DDR2_D1 8 GND
9 GND 10 DDR2_DM0 11 DDR2_DQS0_N 12 GND
13 DDR2_DQS0_P 14 DDR2_D6 15 GND 16 DDR2_D7
17 DDR2_D2 18 GND 19 DDR2_D3 20 DDR2_D12
21 GND 22 DDR2_D13 23 DDR2_D8 24 GND
25 DDR2_D9 26 DDR2_DM1 27 GND 28 GND
29 DDR2_DOS1_N 30 DDR2_CK0_P 31 DDR2_DOS1_P 32 DDR2_CK0_N
33 GND 34 GND 35 DDR2_D10 36 DDR2_D14
37 DDR2_D11 38 DDR2_D15 39 GND 40 GND
41 GND 42 GND 43 DDR2_D16 44 DDR2_D20
45 DDR2_D17 46 DDR2_D21 47 GND 48 GND
49 DDR2_DQS2_N 50 NC 51 DDR2_DQS2_P 52 DDR2_DM2
53 GND 54 GND 55 DDR2_D18 56 DDR2_D22
57 DDR2_D19 58 DDR2_D23 59 GND 60 GND
61 DDR2_D24 62 DDR2_D28 63 DDR2_D25 64 DDR2_D29
65 GND 66 GND 67 DDR2_DM3 68 DDR2_DQS3_N
69 NC 70 DDR2_DQS3_P 71 GND 72 GND
73 DDR2_D26 74 DDR2_D30 75 DDR2_D27 76 DDR2_D31
77 GND 78 GND 79 DDR2_CKE0 80 DDR2_CKE0
81 1.8V 82 1.8V 83 NC 84 NC
85 DDR2_BA2 86 NC 87 1.8V 88 1.8V
89 DDR2_A12 90 DDR2_A11 91 DDR2_A9 92 DDR2_A7
93 DDR2_A8 94 DDR2_A6 95 1.8V 96 1.8V
97 DDR2_A5 98 DDR2_A4 99 DDR2_A3 100 DDR2_A2
101 DDR2_A1 102 DDR2_A0 103 1.8V 104 1.8V
105 DDR2_A10 106 DDR2_BA1 107 DDR2_BA0 108 DDR2_RAS_B
109 DDR2_WE_B 110 DDR2_CS0_B 111 1.8V 112 1.8V
113 DDR2_CAS_B 114 DDR2_ODT0 115 DDR2_CS1_B 116 DDR2_A13
117 1.8V 118 1.8V 119 DDR2_ODT1 120 NC
121 GND 122 GND 123 DDR2_D32 124 DDR2_D36
125 DDR2_D33 126 DDR2_D37 127 GND 128 GND
129 DDR2_DQS4_N 130 DDR2_DDM4 131 DDR2_DQS4_P 132 GND
133 GND 134 DDR2_D38 135 DDR2_D34 136 DDR2_D30
137 DDR2_D35 138 GND 139 GND 140 DDR2_D44
141 DDR2_D40 142 DDR2_D44 143 DDR2_D41 144 GND
145 GND 146 DDR2_DQS5_N 147 DDR2_DM5 148 DDR2_DQS5_P
149 GND 150 GND 151 DDR2_D42 152 DDR2_D46
153 DDR2_D43 154 DDR2_D47 155 GND 156 GND
157 DDR2_D48 158 DDR2_D52 159 DDR2_D49 160 DDR2_D53
161 GND 162 GND 163 NC 164 DDR2_CK1_P
165 GND 166 DDR2_CK1_N 167 DDR2_DQ56_N 168 GND
169 DDR2_DQ56_P 170 DDR2_DM6 171 GND 172 GND
173 DDR2_D50 174 DDR2_D54 175 DDR2_D51 176 DDR2_D55
177 GND 178 GND 179 DDR2_D56 180 DDR2_D60
181 DDR2_D57 182 DDR2_D61 183 GND 184 GND
185 DDR2_DM7 186 DDR2_DQS7_N 187 GND 188 DDR2_DQS7_P
189 DDR2_D58 190 GND 191 DDR2_D59 192 DDR2_D62
193 GND 194 DDR2_D63 195 DDR2_SDA 196 GND
197 DDR2_SDL 198 GND 199 1.8 V 200 GND