DLPU040B October   2016  – March 2023 DLP650LNIR , DLPC410

 

  1.   DLP Discovery 4100 Development Platform User’s Guide
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Welcome
  4. 2Overview
    1. 2.1 The DLP Discovery 4100 Development Platform
    2. 2.2 DLP Discovery 4100 Development Platform Photo
    3. 2.3 Key Components
      1. 2.3.1  Xilinx Virtex 5 APPSFPGA
      2. 2.3.2  DLPC410 - Digital Controller for DLP Discovery 4100 Chipset
      3. 2.3.3  DLPA200 - DMD Micromirror Driver
      4. 2.3.4  DLPR410 - Configuration PROM for DLPC410 Controller
      5. 2.3.5  APPSFPGA Flash Configuration PROM
      6. 2.3.6  DMD Connectors
      7. 2.3.7  USB Controller
      8. 2.3.8  50-MHz Oscillator
      9. 2.3.9  DDR2 SODIMM Connector
      10. 2.3.10 Connectors
        1. 2.3.10.1 JTAG Header H1
        2. 2.3.10.2 Mictor Connectors
        3. 2.3.10.3 GPIO Connectors
      11. 2.3.11 Battery
      12. 2.3.12 Power Supplies
        1. 2.3.12.1 J14 Power Connector
        2. 2.3.12.2 J14 Power Connector
        3. 2.3.12.3 REG. 0.9 V
        4. 2.3.12.4 REG. 1.0 V
        5. 2.3.12.5 REG. 1.8 V
        6. 2.3.12.6 REG. 2.5 V
        7. 2.3.12.7 REG. 3.3 V
        8. 2.3.12.8 REG. 12 V
  5. 3Hardware Overview and Setup
    1. 3.1 Getting Started
    2. 3.2 User Connectors and I/O
      1. 3.2.1  J12 Input Power Connector
      2. 3.2.2  J18 Input Power Connector
      3. 3.2.3  J1 USB Connector Pinout
      4. 3.2.4  J3 USB GPIO
      5. 3.2.5  J6 GPIO_A Connector
      6. 3.2.6  J8 DLPC410 Mictor Connector
      7. 3.2.7  J9 USB/APPSFPGA Mictor Connector
      8. 3.2.8  J13 DMD Flex 1 Connector
      9. 3.2.9  J14 DMD Flex 2 Connector
      10. 3.2.10 J15 DDR2 SODIMM Connector
      11. 3.2.11 J16, J17 EXP Connectors
      12. 3.2.12 H1 Xilinx FPGA JTAG Header
    3. 3.3 Configuration Jumpers
      1. 3.3.1 J2 – EXP Voltage Select
      2. 3.3.2 J4 – APPSFPGA Revision Select
      3. 3.3.3 J5 – Shared USB Signal Enable/Disable
      4. 3.3.4 J7 – USB EEPROM Programming Header
      5. 3.3.5 J10 – DLPA200 B Output Enable
    4. 3.4 Switches
      1. 3.4.1 SW1 - APPSFPGA Functional Switches
      2. 3.4.2 SW2 - APPSFPGA Reset
      3. 3.4.3 SW3 - DMD Power Float (Park)
      4. 3.4.4 SW4 - Input Power On/Off
    5. 3.5 Power and Status LEDs
      1. 3.5.1 D1 – USB Connection Indicator
      2. 3.5.2 D2 and D16 – APPSFPGA Done
      3. 3.5.3 D3 and D17 – DLPC410 Done
      4. 3.5.4 D9 – DDC_LED0
      5. 3.5.5 D10 – DDC_LED1
      6. 3.5.6 D11 – VLED0
      7. 3.5.7 D12 – VLED1
    6. 3.6 Test Points
  6. 4Software
    1. 4.1 Overview
      1. 4.1.1 Software Overview
        1. 4.1.1.1 DMD Image Control
        2. 4.1.1.2 Image Commands
    2. 4.2 DLP Discovery 4100 Operation
      1. 4.2.1 Quick Start Guide on Operation
      2. 4.2.2 74
    3. 4.3 Graphical User Interface
      1. 4.3.1 Menu Bar
        1. 4.3.1.1 File Menu
        2. 4.3.1.2 View Menu
        3. 4.3.1.3 DMD Menu
        4. 4.3.1.4 Execution Menu
        5. 4.3.1.5 Test Patterns Menu
        6. 4.3.1.6 Help Menu
      2. 4.3.2 Toolbar
        1. 4.3.2.1 File Menu Buttons
        2. 4.3.2.2 Run, Run Once, Loop Break, Step and Stop Controls
        3. 4.3.2.3 Set Start and End Buttons
        4. 4.3.2.4 Help Button
      3. 4.3.3 Script Commands Window
        1. 4.3.3.1 Load Tab
        2. 4.3.3.2 Reset Tab
        3. 4.3.3.3 Clear Tab
        4. 4.3.3.4 Float Tab
        5. 4.3.3.5 Control Tab
      4. 4.3.4 Status Window
      5. 4.3.5 Script Window
        1. 4.3.5.1 Inserting Commands
        2. 4.3.5.2 Moving Commands
        3. 4.3.5.3 Deleting Commands
    4. 4.4 Script and Status Operations
      1. 4.4.1 Saving Scripts and Statuses
        1. 4.4.1.1 Saving a Script
        2. 4.4.1.2 Saving a Status
      2. 4.4.2 Printing Scripts and Statuses
        1. 4.4.2.1 Printing a Script
        2. 4.4.2.2 Printing a Status
      3. 4.4.3 Opening Scripts and Statuses
      4. 4.4.4 Creating New Scripts and Statuses
        1. 4.4.4.1 Creating a New Script
        2. 4.4.4.2 Creating a New Status
    5. 4.5 DLPC410 Control Window
    6. 4.6 Test Patterns Window
    7. 4.7 About Box
    8. 4.8 Links
  7. 5Related Documentation
  8. 6Appendix
    1. 6.1 Abbreviations and Acronyms
    2. 6.2 Notational Conventions
      1. 6.2.1 Information About Cautions and Warnings
  9. 7Revision History

2 Overview

DLP Discovery 4100 is a group of six evaluation modules which, when paired together, create a highly flexible platform to learn, experiment and develop with DLP technology. At the heart of the platform is the DLPLCRC410EVM controller board. The DLPLCRC410EVM board includes the DLPC410, DLPR410, DLPA200, digital receiver, flash, power management circuits, and supporting digital logic. To give designers scalability to port their DLP design work across multiple DMD devices, the DLPLCRC410EVM operates with any of the following five DMD EVMs:

  • DLPLCR65NEVM: includes DLP650LNIR DMD board, DLP650LNIR DMD, and one flex cable
  • DLPLCR70EVM: includes the DLP7000 DMD board, DLP7000 DMD, and one flex cable
  • DLPLCR70UVEVM: includes the DLP7000UV DMD board, DLP7000UV DMD, and one flex cable
  • DLPLCR95EVM: includes the DLP9500 DMD board, DLP9500 DMD, and two flex cables
  • DLPLCR95UVEVM: includes the DLP9500UV DMD board, DLP9500UV DMD, and two flex cables

When the DLPLCRC410EVM is connected to any of the DMD EVMs, the DLPC410, Applications FPGA, and Software GUI recognizes and provides the proper signals and timing to the attached DMD. Out of the box, the DLPLCRC410EVM delivers a small set of scrolling test patterns which allow customers to evaluate their optical designs for related optical performance. When desired, these scrolling test patterns can be stopped keeping a selected pattern constant. If these patterns are not sufficient, the PC-based software GUI can be used. The GUI program allows binary pattern data to be downloaded via USB to the on-board Applications FPGA (APPSFPGA). The Applications FPGA sends the data to the DLPC410 which then displays the image or pattern on the DMD.

The Xilinx Virtex 5 (LX50) APPSFPGA provides a user programmable platform for developing custom applications. The APPSFPGA is connected to EXP Expansion Connectors for custom interfaces. An onboard USB interface provides a convenient interface for development. Connections for DDR2 SODIMM memory and SPI Flash Memory to the Application FPGA are also included. A Cypress CY7C68013A USB controller is included for customer USB control applications. The source code for the APPSFPGA is provided on TI.COM to provide VHDL savvy customers a reference to leverage for their own development.

Users of the D4100 have the ability to work with visible, UV and NIR light with pixel-level precision and fast pattern rates. The D4100 offers developers a flexible platform to design products to fit many applications using the proven reliability of DLP technology. As previously mentioned, the five DMD-based EVMs enable five distinct DMD options: two in the visible spectrum, two in the UV spectrum, and one in the NIR spectrum. The EVMs, DMDs, and select performance data are shown in #GUID-BF225118-F201-4C32-BCBC-FF8C33F858F1/T4709747-19:

Table 2-1 D4100 Platform EVMs and DMD Types
EVM DMD PRODUCT FOLDER DMD COLUMNS DMD ROWS RESET MAX BINARY PATTERN RATE (Hz) DATA BUS WIDTH
GLOBAL RESET PHASED RESET
DLPLCR95EVM DLP9500 0.95 1080p 1920 1080 17,636 23,148 64
DLPLCR95UVEVM DLP9500UV 0.95 UV 1080p
DLPLCR70EVM DLP7000 0.7 XGA 1024 768 22,614 32,552 32
DLPLCR70UVEVM DLP7000UV 0.7 UV XGA
DLPLCR65NEVM DLP650LNIR .65 NIR WXGA 1280 800 10,800 12,500 16

The D4100 Platform combines the high performance D4100 chip set with a user programmable Application FPGA (APPSFPGA).

The Xilinx Virtex 5 (LX50) APPSFPGA provides a user programmable platform for developing custom applications. The APPSFPGA is connected to EXP Expansion Connectors for custom interfaces. An onboard USB interface provides a convenient interface for rapid prototyping. Connections for DDR2 SO-DIMM memory and SPI Flash Memory to the Application FPGA are included for customer use. A Cypress CY7C68013A USB controller is included for customer USB control applications.

This document helps facilitate use of the D4100 Platform and provides a hardware reference design details for DLPLCRC410EVM.