JAJSG16 August 2018 PGA305
PRODUCTION DATA.
Standard good layout practices must be used when designing a board to test the PGA305 device. Depending on the number of layers in the board, one or more GND planes should be inserted as internal layers. However, given the limited number of external components required for an application using the PGA305 device and the number of NC pins in the device, so it is possible to design a simple two-layer board. In addition, the PWR decoupling capacitor must be placed as close to the pin as possible. In a similar way, the 100-nF recommended capacitors for the AVDD and DVDD regulators as well as the 10-nF to 1000-nF recommended capacitor for REFCAP must be placed as close to their respective pins as possible.
Depending on the application, the signal traces for FB–, FB+, COMP, and OUT must be routed so that they do not cross one another to minimize coupling.