JAJU446A
December 2017 – January 2022
概要
Resources
特長
アプリケーション
5
1
System Description
1.1
Key System Specifications
2
System Overview
2.1
Block Diagram
2.2
System-Level Description
2.3
Highlighted Products
2.3.1
Analog Signal Chain
2.3.1.1
LMH5401
2.3.1.2
LHM6401
2.3.1.3
BUF802
2.3.2
Clock
2.3.2.1
LMK61E2
2.3.2.2
LMK04828
2.3.2.3
LMX2594
2.3.3
Power
2.3.3.1
TPS82130
2.3.3.2
TPS7A84
2.4
System Design Theory
2.4.1
High-Speed, Low-Phase Noise Clock Generation
2.4.2
Channel-to-Channel Skew
2.4.3
Deterministic Latency
2.4.3.1
Importance of Deterministic Latency
2.4.4
Analog Front End
2.4.5
Multichannel System Power Requirement
2.4.6
Hardware Programming
3
Circuit Design
3.1
Analog Input Front End
3.1.1
High-Input Impedance Buffer Implementation Using the BUF802
3.2
High-Speed Multichannel Clocking
3.3
Power Supply Section
3.3.1
DC-DC
3.3.1.1
How to Set 2.1-V Output Voltage
3.3.2
LDOs
4
Host Interface
5
Hardware Functional Block
6
Getting Started Application GUI
7
Testing and Results
7.1
Test Setup and Test Plan
44
7.2
SNR Measurement Test
7.3
Channel-to-Channel Skew Measurement Test
7.4
Performance Test Result
7.5
Multichannel Skew Measurement
7.6
49
8
Design Files
8.1
Schematics
8.2
Bill of Materials
8.3
Altium Project
8.4
Gerber Files
8.5
Assembly Drawings
9
Software Files
10
Related Documentation
10.1
Trademarks
11
About the Authors
11.1
Acknowledgment
12
Revision History
10
Related Documentation
Texas Instruments,
Cascaded LMH5401 and LMH6401 Reference Design
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JESD204B Deterministic Latency
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JESD204B multi-device synchronization: Breaking down the requirements
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Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers
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50-Ohm 2-GHz Oscilloscope Front-end Reference Design
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ADC12DJ3200 Evaluation Module
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TSW14J56 JESD204B High-Speed Data Capture and Pattern Generator Card
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TSW14J57 JESD204B High-Speed Data Capture and Pattern Generator Card User's Guide