JAJU446A December 2017 – January 2022
High-performance data converters require high-precision clocking with ultra-low phase noise. The generation of these clocks and their distribution to various components through PCBs, connectors, and other devices requires impedance matching, signal power isolation, and high fan-out clock buffering to drive a receiver from a long distance. The clock generation architecture can vary depending on system requirements. Clock generation and distribution are typical in low-channel-count systems such as oscilloscopes and can be performed using a single device; however, careful routing and clock-to-clock matching is necessary to obtain optimum performance.
Most high-speed digitizers or DSOs feature only a few channels. Synchronizing the sample clock in a multichannel system is necessary in applications that require tens or hundreds of channels and time correlation between these channels. Clock synchronization in a system with just a few channels is very challenging in and of itself and even more complex when working with an increased channel count.
This reference design uses the clocking solution provided in Multichannel JESD204B 15-GHz Clocking Reference Design for DSO, Radar, and 5G Wireless Testers.